scsi: ufs: host: mediatek: Assign power mode userdata before FASTAUTO mode change

[ Upstream commit 979feee0cf43b32d288931649d7c6d9a5524ea55 ]

Assign power mode userdata settings before transitioning to FASTAUTO
power mode. This ensures that default timeout values are set for various
parameters, enhancing the reliability and performance of the power mode
change process.

Signed-off-by: Alice Chao <alice.chao@mediatek.com>
Reviewed-by: Peter Wang <peter.wang@mediatek.com>
Signed-off-by: Peter Wang <peter.wang@mediatek.com>
Link: https://lore.kernel.org/r/20250811131423.3444014-7-peter.wang@mediatek.com
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/ufs/host/ufs-mediatek.c b/drivers/ufs/host/ufs-mediatek.c
index 4171fa672450d72ded00cd712ed95aa38cf872bb..ada21360aa270e963a436d225b3497acd637c0e7 100644 (file)
--- a/drivers/ufs/host/ufs-mediatek.c
+++ b/drivers/ufs/host/ufs-mediatek.c
@@ -1349,6 +1349,28 @@ static int ufs_mtk_pre_pwr_change(struct ufs_hba *hba,
                ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXHSADAPTTYPE),
                               PA_NO_ADAPT);
 
+               if (!(hba->quirks & UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING)) {
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0),
+                                       DL_FC0ProtectionTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1),
+                                       DL_TC0ReplayTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2),
+                                       DL_AFC0ReqTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA3),
+                                       DL_FC1ProtectionTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA4),
+                                       DL_TC1ReplayTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA5),
+                                       DL_AFC1ReqTimeOutVal_Default);
+
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalFC0ProtectionTimeOutVal),
+                                       DL_FC0ProtectionTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalTC0ReplayTimeOutVal),
+                                       DL_TC0ReplayTimeOutVal_Default);
+                       ufshcd_dme_set(hba, UIC_ARG_MIB(DME_LocalAFC0ReqTimeOutVal),
+                                       DL_AFC0ReqTimeOutVal_Default);
+               }
+
                ret = ufshcd_uic_change_pwr_mode(hba,
                                        FASTAUTO_MODE << 4 | FASTAUTO_MODE);