arm: Auto-vectorization for MVE: vaddv

This patch adds support for the reduc_plus_scal optab with MVE, which
maps to the vaddv instruction.

It moves the reduc_plus_scal_<mode> expander from neon.md to
vec-common.md and adds support for MVE to it.

Since vaddv uses a 32-bits accumulator, we have to truncate it's
result.

For instance:
int32_t test__s8x16 (int8_t *a) {
  int i;
  int8_t result = 0;
  for (i=0; i<16; i++) {
    result += a[i];
  }
  return result;
}
is compiled into:
  vldrb.8 q3, [r0]
  vaddv.s8        r0, q3
  sxtb    r0, r0
  bx      lr

If we used uint8_t instead of int8_t, we still use vaddv.s8        r0, q3,
but truncate with uxtb    r0, r0.

2021-05-25  Christophe Lyon  <christophe.lyon@linaro.org>

	gcc/
	* config/arm/mve.md (mve_vaddvq_<supf><mode>): Prefix with '@'.
	* config/arm/neon.md (reduc_plus_scal_<mode>): Move to ..
	* config/arm/vec-common.md: .. here. Add support for MVE.

	gcc/testsuite/
	* gcc.target/arm/simd/mve-vaddv-1.c: New test.

diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 133ebe93cf3f60168e5dbc9866a0114110b41444..0a6ba80c99dbb5fe3cbaa23b08f5ff6f02e9e7d4 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -464,7 +464,7 @@
 ;;
 ;; [vaddvq_s, vaddvq_u])
 ;;
-(define_insn "mve_vaddvq_<supf><mode>"
+(define_insn "@mve_vaddvq_<supf><mode>"
   [
    (set (match_operand:SI 0 "s_register_operand" "=Te")
        (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")]

diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
index 977adef5490f565ed2fd111a3217b2e9d8e33216..6a6573317cf7b80b15bb4d5d53633b9a105ba50c 100644 (file)
--- a/gcc/config/arm/neon.md
+++ b/gcc/config/arm/neon.md
@@ -1161,19 +1161,6 @@
   DONE;
 })
 
-(define_expand "reduc_plus_scal_<mode>"
-  [(match_operand:<V_elem> 0 "nonimmediate_operand")
-   (match_operand:VQ 1 "s_register_operand")]
-  "ARM_HAVE_NEON_<MODE>_ARITH && !BYTES_BIG_ENDIAN"
-{
-  rtx step1 = gen_reg_rtx (<V_HALF>mode);
-
-  emit_insn (gen_quad_halves_plus<mode> (step1, operands[1]));
-  emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1));
-
-  DONE;
-})
-
 (define_expand "reduc_plus_scal_v2di"
   [(match_operand:DI 0 "nonimmediate_operand")
    (match_operand:V2DI 1 "s_register_operand")]

diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md
index e8b2901b0069c29260f5e9d3e8ff0c8ba1cf9316..8e35151da46780d4d6243d4245ea1e1fadb454ae 100644 (file)
--- a/gcc/config/arm/vec-common.md
+++ b/gcc/config/arm/vec-common.md
@@ -539,3 +539,29 @@
     emit_insn (gen_mve_vst4q<mode> (operands[0], operands[1]));
   DONE;
 })
+
+(define_expand "reduc_plus_scal_<mode>"
+  [(match_operand:<V_elem> 0 "nonimmediate_operand")
+   (match_operand:VQ 1 "s_register_operand")]
+  "ARM_HAVE_<MODE>_ARITH
+   && !(TARGET_HAVE_MVE && FLOAT_MODE_P (<MODE>mode))
+   && !BYTES_BIG_ENDIAN"
+{
+  if (TARGET_NEON)
+    {
+      rtx step1 = gen_reg_rtx (<V_HALF>mode);
+
+      emit_insn (gen_quad_halves_plus<mode> (step1, operands[1]));
+      emit_insn (gen_reduc_plus_scal_<V_half> (operands[0], step1));
+    }
+  else
+    {
+      /* vaddv generates a 32 bits accumulator.  */
+      rtx op0 = gen_reg_rtx (SImode);
+
+      emit_insn (gen_mve_vaddvq (VADDVQ_S, <MODE>mode, op0, operands[1]));
+      emit_move_insn (operands[0], gen_lowpart (<V_elem>mode, op0));
+    }
+
+  DONE;
+})

diff --git a/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c
new file mode 100644 (file)
index 0000000..b6b0bc3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/simd/mve-vaddv-1.c
@@ -0,0 +1,26 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <stdint.h>
+
+#define FUNC(SIGN, TYPE, BITS, NB)                                     \
+  TYPE##32_t test_ ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t *a) { \
+    int i;                                                             \
+    TYPE##BITS##_t result = 0;                                         \
+    for (i=0; i<NB; i++) {                                             \
+      result += a[i];                                                  \
+    }                                                                  \
+    return result;                                                     \
+}
+
+/* 128-bit vectors.  */
+FUNC(s, int, 8, 16)
+FUNC(u, uint, 8, 16)
+FUNC(s, int, 16, 8)
+FUNC(u, uint, 16, 8)
+FUNC(s, int, 32, 4)
+FUNC(u, uint, 32, 4)
+
+/* { dg-final { scan-assembler-times {vaddv\.s} 6 } } */