IRExpr *s390rm;
IRExpr *irrm;
- vassert(s390_host_has_pfpo);
/* The dfp/bfp rounding mode is stored in bits [60:63] of GR 0
when PFPO insn is called. So, extract the bits at [60:63] */
assign(rm_bits, binop(Iop_And32, get_gpr_w1(0), mkU32(0xf)));
IRTemp dst18 = newTemp(Ity_F128);
IRExpr *irrm;
- vassert(s390_host_has_pfpo);
+ if (! s390_host_has_pfpo) {
+ emulation_failure(EmFail_S390X_pfpo);
+ goto done;
+ }
assign(gr0, get_gpr_w1(0));
/* get function code */
s390_cc_thunk_put1d128Z(S390_CC_OP_PFPO_128, src18, gr0);
next_insn_if(binop(Iop_CmpEQ32, mkexpr(fn), mkU32(S390_PFPO_D128_TO_F128)));
+ done:
return "pfpo";
}
return "Instruction stckf is not supported on this host";
case EmFail_S390X_ecag:
return "Instruction ecag is not supported on this host";
+ case EmFail_S390X_pfpo:
+ return "Instruction pfpo is not supported on this host";
case EmFail_S390X_fpext:
return "Encountered an instruction that requires the floating "
"point extension facility.\n"
/* ecag insn is not supported on this host */
EmFail_S390X_ecag,
+ /* pfpo insn is not supported on this host */
+ EmFail_S390X_pfpo,
+
/* insn needs floating point extension facility which is not
available on this host */
EmFail_S390X_fpext,