realtek: mdio: use register field indentation

Make clearer which field belongs to which register. For this
sort the fields below the registers and use indentation.

Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de>
Link: https://github.com/openwrt/openwrt/pull/22075
Signed-off-by: Robert Marko <robimarko@gmail.com>

diff --git a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
index 1a70e5d3a03c0db43098f5a9c3caf2a93d206d88..e38f98914e5372c72e2231739cdb94e772b08c10 100644 (file)
--- a/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
+++ b/target/linux/realtek/files-6.12/drivers/net/mdio/mdio-realtek-otto.c
@@ -28,47 +28,47 @@
 
 #define RTMDIO_PHY_POLL_MMD(dev, reg, bit)     ((bit << 21) | (dev << 16) | reg)
 
-/* MDIO bus registers */
+/* MDIO bus registers/fields */
 #define RTMDIO_RUN                             BIT(0)
 
-#define RTMDIO_838X_CMD_FAIL                   0
-#define RTMDIO_838X_CMD_READ_C22               0
-#define RTMDIO_838X_CMD_READ_C45               BIT(1)
-#define RTMDIO_838X_CMD_WRITE_C22              BIT(2)
-#define RTMDIO_838X_CMD_WRITE_C45              BIT(1) | BIT(2)
-#define RTMDIO_838X_CMD_MASK                   GENMASK(2, 0)
 #define RTMDIO_838X_PHY_PATCH_DONE             BIT(15)
 #define RTMDIO_838X_SMI_GLB_CTRL               (0xa100)
 #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_0      (0xa1b8)
 #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_1      (0xa1bc)
+#define   RTMDIO_838X_CMD_FAIL                 0
+#define   RTMDIO_838X_CMD_READ_C22             0
+#define   RTMDIO_838X_CMD_READ_C45             BIT(1)
+#define   RTMDIO_838X_CMD_WRITE_C22            BIT(2)
+#define   RTMDIO_838X_CMD_WRITE_C45            BIT(1) | BIT(2)
+#define   RTMDIO_838X_CMD_MASK                 GENMASK(2, 0)
 #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_2      (0xa1c0)
 #define RTMDIO_838X_SMI_ACCESS_PHY_CTRL_3      (0xa1c4)
 #define RTMDIO_838X_SMI_POLL_CTRL              (0xa17c)
 #define RTMDIO_838X_SMI_PORT0_5_ADDR_CTRL      (0xa1c8)
 
-#define RTMDIO_839X_CMD_FAIL                   BIT(1)
-#define RTMDIO_839X_CMD_READ_C22               0
-#define RTMDIO_839X_CMD_READ_C45               BIT(2)
-#define RTMDIO_839X_CMD_WRITE_C22              BIT(3)
-#define RTMDIO_839X_CMD_WRITE_C45              BIT(2) | BIT(3)
-#define RTMDIO_839X_CMD_MASK                   GENMASK(3, 0)
 #define RTMDIO_839X_PHYREG_CTRL                        (0x03E0)
 #define RTMDIO_839X_PHYREG_PORT_CTRL           (0x03E4)
 #define RTMDIO_839X_PHYREG_ACCESS_CTRL         (0x03DC)
+#define   RTMDIO_839X_CMD_FAIL                 BIT(1)
+#define   RTMDIO_839X_CMD_READ_C22             0
+#define   RTMDIO_839X_CMD_READ_C45             BIT(2)
+#define   RTMDIO_839X_CMD_WRITE_C22            BIT(3)
+#define   RTMDIO_839X_CMD_WRITE_C45            BIT(2) | BIT(3)
+#define   RTMDIO_839X_CMD_MASK                 GENMASK(3, 0)
 #define RTMDIO_839X_PHYREG_DATA_CTRL           (0x03F0)
 #define RTMDIO_839X_PHYREG_MMD_CTRL            (0x03F4)
 #define RTMDIO_839X_SMI_PORT_POLLING_CTRL      (0x03fc)
 #define RTMDIO_839X_SMI_GLB_CTRL               (0x03f8)
 
-#define RTMDIO_930X_CMD_FAIL                   BIT(25)
-#define RTMDIO_930X_CMD_READ_C22               0
-#define RTMDIO_930X_CMD_READ_C45               BIT(1)
-#define RTMDIO_930X_CMD_WRITE_C22              BIT(2)
-#define RTMDIO_930X_CMD_WRITE_C45              BIT(1) | BIT(2)
-#define RTMDIO_930X_CMD_MASK                   GENMASK(2, 0) | BIT(25)
 #define RTMDIO_930X_SMI_GLB_CTRL               (0xCA00)
 #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_0      (0xCB70)
 #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_1      (0xCB74)
+#define   RTMDIO_930X_CMD_FAIL                 BIT(25)
+#define   RTMDIO_930X_CMD_READ_C22             0
+#define   RTMDIO_930X_CMD_READ_C45             BIT(1)
+#define   RTMDIO_930X_CMD_WRITE_C22            BIT(2)
+#define   RTMDIO_930X_CMD_WRITE_C45            BIT(1) | BIT(2)
+#define   RTMDIO_930X_CMD_MASK                 GENMASK(2, 0) | BIT(25)
 #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_2      (0xCB78)
 #define RTMDIO_930X_SMI_ACCESS_PHY_CTRL_3      (0xCB7C)
 #define RTMDIO_930X_SMI_PORT0_15_POLLING_SEL   (0xCA08)
@@ -80,17 +80,17 @@
 #define RTMDIO_930X_SMI_10G_POLLING_REG10_CFG  (0xCBBC)
 #define RTMDIO_930X_SMI_PORT0_5_ADDR_CTRL      (0xCB80)
 
-#define RTMDIO_931X_CMD_FAIL                   BIT(1)
-#define RTMDIO_931X_CMD_READ_C22               0
-#define RTMDIO_931X_CMD_READ_C45               BIT(3)
-#define RTMDIO_931X_CMD_WRITE_C22              BIT(4)
-#define RTMDIO_931X_CMD_WRITE_C45              BIT(3) | BIT(4)
-#define RTMDIO_931X_CMD_MASK                   GENMASK(4, 0)
 #define RTMDIO_931X_SMI_PORT_POLLING_CTRL      (0x0CCC)
 #define RTMDIO_931X_SMI_INDRT_ACCESS_BC_CTRL   (0x0C14)
 #define RTMDIO_931X_SMI_GLB_CTRL0              (0x0CC0)
 #define RTMDIO_931X_SMI_GLB_CTRL1              (0x0CBC)
 #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_0    (0x0C00)
+#define   RTMDIO_931X_CMD_FAIL                 BIT(1)
+#define   RTMDIO_931X_CMD_READ_C22             0
+#define   RTMDIO_931X_CMD_READ_C45             BIT(3)
+#define   RTMDIO_931X_CMD_WRITE_C22            BIT(4)
+#define   RTMDIO_931X_CMD_WRITE_C45            BIT(3) | BIT(4)
+#define   RTMDIO_931X_CMD_MASK                 GENMASK(4, 0)
 #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_1    (0x0C04)
 #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_2    (0x0C08)
 #define RTMDIO_931X_SMI_INDRT_ACCESS_CTRL_3    (0x0C10)