phy: qcom: qusb2: Add QCS615 QUSB2 PHY support

Add support for QCS615 QUSB2 PHY by introducing platform-specific
initialization table and register layout. The implementation reuses
the IPQ6018 register layout and defines QCS615-specific tuning
parameters for proper USB PHY operation.

Taken from Linux commit 8adbf20e0502 ("phy: qcom-qusb2: Add support for QCS615")

Signed-off-by: Balaji Selvanathan <balaji.selvanathan@oss.qualcomm.com>
Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://patch.msgid.link/20260213-talos_usb-v1-3-4c4355d61437@oss.qualcomm.com
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>

diff --git a/drivers/phy/qcom/phy-qcom-qusb2.c b/drivers/phy/qcom/phy-qcom-qusb2.c
index 9e821365c151c56f9b488b225aafa5e1f368b831..6278171b100d8740cd26cafd9cd2013bd1baf6fb 100644 (file)
--- a/drivers/phy/qcom/phy-qcom-qusb2.c
+++ b/drivers/phy/qcom/phy-qcom-qusb2.c
@@ -176,6 +176,19 @@ static const unsigned int sm6115_regs_layout[] = {
        [QUSB2PHY_PORT_POWERDOWN] = 0xb4, [QUSB2PHY_INTR_CTRL] = 0xbc,
 };
 
+static const unsigned int ipq6018_regs_layout[] = {
+       [QUSB2PHY_PLL_STATUS] = 0x38,
+       [QUSB2PHY_PORT_TUNE1] = 0x80,
+       [QUSB2PHY_PORT_TUNE2] = 0x84,
+       [QUSB2PHY_PORT_TUNE3] = 0x88,
+       [QUSB2PHY_PORT_TUNE4] = 0x8C,
+       [QUSB2PHY_PORT_TUNE5] = 0x90,
+       [QUSB2PHY_PORT_TEST1] = 0x98,
+       [QUSB2PHY_PORT_TEST2] = 0x9C,
+       [QUSB2PHY_PORT_POWERDOWN] = 0xB4,
+       [QUSB2PHY_INTR_CTRL] = 0xBC,
+};
+
 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
        QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8),
        QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
@@ -189,6 +202,19 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
        QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
 };
 
+static const struct qusb2_phy_init_tbl qcs615_init_tbl[] = {
+       QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xc8),
+       QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3),
+       QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83),
+       QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0),
+       QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
+       QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
+       QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
+       QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14),
+       QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f),
+       QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
+};
+
 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = {
        QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03),
        QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
@@ -260,6 +286,16 @@ static const struct qusb2_phy_cfg sdm660_phy_cfg = {
        .autoresume_en = BIT(3),
 };
 
+static const struct qusb2_phy_cfg qcs615_phy_cfg = {
+       .tbl = qcs615_init_tbl,
+       .tbl_num = ARRAY_SIZE(qcs615_init_tbl),
+       .regs = ipq6018_regs_layout,
+
+       .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN),
+       .mask_core_ready = PLL_LOCKED,
+       .autoresume_en = BIT(0),
+};
+
 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = {
        .tbl = qusb2_v2_init_tbl,
        .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl),
@@ -467,6 +503,8 @@ static const struct udevice_id qusb2phy_ids[] = {
        { .compatible = "qcom,qusb2-phy" },
        { .compatible = "qcom,qcm2290-qusb2-phy",
          .data = (ulong)&sm6115_phy_cfg },
+       { .compatible = "qcom,qcs615-qusb2-phy",
+         .data = (ulong)&qcs615_phy_cfg },
        { .compatible = "qcom,sdm660-qusb2-phy",
          .data = (ulong)&sdm660_phy_cfg },
        { .compatible = "qcom,sm6115-qusb2-phy",