PCI: dwc: Use pcie_get_link_speed() helper for safe array access

Replace direct indexing of pcie_link_speed[] with the new helper
pcie_get_link_speed() in all DesignWare core and glue drivers. This
ensures that out-of-range generation numbers do not cause out-of-bounds
accesses when the helper returns PCI_SPEED_UNKNOWN, and prepares for
the removal of the range check in of_pci_get_max_link_speed().

The actual validation of the "max-link-speed" DT property (e.g., fallback
to a safe default and warning) is added in subsequent patches for each
driver that reads the property.

Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260313165522.123518-3-18255117159@163.com

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 6ae6189e9b8a9021c99ece17504834650debd86b..0e05c5280344231d64327a34242ff8ef0f3a1301 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1081,7 +1081,7 @@ static void dw_pcie_program_presets(struct dw_pcie_rp *pp, enum pci_bus_speed sp
 static void dw_pcie_config_presets(struct dw_pcie_rp *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-       enum pci_bus_speed speed = pcie_link_speed[pci->max_link_speed];
+       enum pci_bus_speed speed = pcie_get_link_speed(pci->max_link_speed);
 
        /*
         * Lane equalization settings need to be applied for all data rates the

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 5741c09dde7f40487c6da6dfd66f7c8d96a74259..06792ba92aa7ba73c705d0ae199f6415dcffa02f 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -861,7 +861,7 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci)
        ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2);
        ctrl2 &= ~PCI_EXP_LNKCTL2_TLS;
 
-       switch (pcie_link_speed[pci->max_link_speed]) {
+       switch (pcie_get_link_speed(pci->max_link_speed)) {
        case PCIE_SPEED_2_5GT:
                link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT;
                break;

diff --git a/drivers/pci/controller/dwc/pcie-qcom-common.c b/drivers/pci/controller/dwc/pcie-qcom-common.c
index 01c5387e53bfcc54dea2dbcbec21ef56381a3e07..5aa73c6287373fceb21b179e736b51e9b65bf7e6 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom-common.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-common.c
@@ -22,7 +22,7 @@ void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
         * applied.
         */
 
-       for (speed = PCIE_SPEED_8_0GT; speed <= pcie_link_speed[pci->max_link_speed]; speed++) {
+       for (speed = PCIE_SPEED_8_0GT; speed <= pcie_get_link_speed(pci->max_link_speed); speed++) {
                if (speed > PCIE_SPEED_32_0GT) {
                        dev_warn(dev, "Skipped equalization settings for unsupported data rate\n");
                        break;

diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 18460f01b2c67c3aa2383fee8890dc75d1fb6b15..4b7184d4a6fa0955b39edc1a32cc94aa4822818d 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -152,7 +152,7 @@
 #define WAKE_DELAY_US                          2000 /* 2 ms */
 
 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
-               Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
+               Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_get_link_speed(speed)))
 
 #define to_pcie_ep(x)                          dev_get_drvdata((x)->dev)
 
@@ -531,7 +531,7 @@ skip_resources_enable:
 
        qcom_pcie_common_set_equalization(pci);
 
-       if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
+       if (pcie_get_link_speed(pci->max_link_speed) == PCIE_SPEED_16_0GT)
                qcom_pcie_common_set_16gt_lane_margining(pci);
 
        /*

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 67a16af69ddc75fca1b123e70715e692a91a9135..5c7c105bb745fe217bb47f8fe016e5dbaffbc042 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -170,7 +170,7 @@
 #define QCOM_PCIE_CRC8_POLYNOMIAL              (BIT(2) | BIT(1) | BIT(0))
 
 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
-               Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
+               Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_get_link_speed(speed)))
 
 struct qcom_pcie_resources_1_0_0 {
        struct clk_bulk_data *clks;
@@ -320,7 +320,7 @@ static int qcom_pcie_start_link(struct dw_pcie *pci)
 
        qcom_pcie_common_set_equalization(pci);
 
-       if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
+       if (pcie_get_link_speed(pci->max_link_speed) == PCIE_SPEED_16_0GT)
                qcom_pcie_common_set_16gt_lane_margining(pci);
 
        /* Enable Link Training state machine */
@@ -1579,7 +1579,7 @@ static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)
                                ret);
                }
        } else if (pcie->use_pm_opp) {
-               freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]);
+               freq_mbps = pcie_dev_speed_mbps(pcie_get_link_speed(speed));
                if (freq_mbps < 0)
                        return;
 

diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 06571d806ab31fa7d6e2866db1c895764220c8a1..47f08adfbd798f8493242c646e56bd96279f412d 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -310,7 +310,7 @@ static void tegra_pcie_icc_set(struct tegra_pcie_dw *pcie)
        speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, val);
        width = FIELD_GET(PCI_EXP_LNKSTA_NLW, val);
 
-       val = width * PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]);
+       val = width * PCIE_SPEED2MBS_ENC(pcie_get_link_speed(speed));
 
        if (icc_set_bw(pcie->icc_path, Mbps_to_icc(val), 0))
                dev_err(pcie->dev, "can't set bw[%u]\n", val);