[AArch64] Fix TBAA information when lowering NEON loads and stores to gimple

This patch fixes the wrong TBAA information when lowering NEON loads and stores
to gimple that showed up when bootstrapping with UBSAN.

gcc/ChangeLog:

	* config/aarch64/aarch64-builtins.c
	(aarch64_general_gimple_fold_builtin): Change pointer alignment and
	alias.

gcc/testsuite/ChangeLog:

	* gcc.target/aarch64/simd/lowering_tbaa.c: New test.

diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c
index 5053bf0f8fd6638bf84a6df06c0987a0216b69e7..416b4fc2dea7bb52643dbbcc8ef5a15dd65ca605 100644 (file)
--- a/gcc/config/aarch64/aarch64-builtins.c
+++ b/gcc/config/aarch64/aarch64-builtins.c
@@ -2670,18 +2670,18 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt,
              = get_mem_type_for_load_store(fcode);
            aarch64_simd_type_info simd_type
              = aarch64_simd_types[mem_type];
-           tree elt_ptr_type = build_pointer_type (simd_type.eltype);
+           tree elt_ptr_type = build_pointer_type_for_mode (simd_type.eltype,
+                                                            VOIDmode, true);
            tree zero = build_zero_cst (elt_ptr_type);
-           gimple_seq stmts = NULL;
-           tree base = gimple_convert (&stmts, elt_ptr_type,
-                                       args[0]);
-           if (stmts)
-             gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+           /* Use element type alignment.  */
+           tree access_type
+             = build_aligned_type (simd_type.itype,
+                                   TYPE_ALIGN (simd_type.eltype));
            new_stmt
              = gimple_build_assign (gimple_get_lhs (stmt),
                                     fold_build2 (MEM_REF,
-                                                 simd_type.itype,
-                                                 base, zero));
+                                                 access_type,
+                                                 args[0], zero));
          }
        break;
 
@@ -2692,18 +2692,17 @@ aarch64_general_gimple_fold_builtin (unsigned int fcode, gcall *stmt,
              = get_mem_type_for_load_store(fcode);
            aarch64_simd_type_info simd_type
              = aarch64_simd_types[mem_type];
-           tree elt_ptr_type = build_pointer_type (simd_type.eltype);
+           tree elt_ptr_type = build_pointer_type_for_mode (simd_type.eltype,
+                                                            VOIDmode, true);
            tree zero = build_zero_cst (elt_ptr_type);
-           gimple_seq stmts = NULL;
-           tree base = gimple_convert (&stmts, elt_ptr_type,
-                                       args[0]);
-           if (stmts)
-             gsi_insert_seq_before (gsi, stmts, GSI_SAME_STMT);
+           /* Use element type alignment.  */
+           tree access_type
+             = build_aligned_type (simd_type.itype,
+                                   TYPE_ALIGN (simd_type.eltype));
            new_stmt
-             = gimple_build_assign (fold_build2 (MEM_REF,
-                                    simd_type.itype,
-                                    base,
-                                    zero), args[1]);
+             = gimple_build_assign (fold_build2 (MEM_REF, access_type,
+                                                 args[0], zero),
+                                    args[1]);
          }
        break;
 

diff --git a/gcc/testsuite/gcc.target/aarch64/simd/lowering_tbaa.c b/gcc/testsuite/gcc.target/aarch64/simd/lowering_tbaa.c
new file mode 100644 (file)
index 0000000..eaeae21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/simd/lowering_tbaa.c
@@ -0,0 +1,30 @@
+/* Tests the TBAA information of lowered AArch64 SIMD loads.  */
+/* { dg-do run } */
+/* { dg-options "-save-temps -O2" } */
+
+#include <arm_neon.h>
+
+void __attribute__((noipa))
+g (float *)
+{
+}
+
+int32x4_t __attribute__((noipa))
+f (void)
+{
+  float a[4] = { 1, 2, 3, 4 };
+  g (a);
+  a[0] = a[1] = a[2] = a[3] = 0;
+  void *volatile ptr = a;
+  return vld1q_s32 ((int32_t *) ptr);
+}
+
+int
+main (void)
+{
+  int32x4_t x = f ();
+  int32x4_t y = vdupq_n_s32 (0);
+  if (__builtin_memcmp (&x, &y, 16) != 0)
+    __builtin_abort ();
+  return 0;
+}