mmc: sdhci-pci-gli: Use PCI AER definitions, not hard-coded values

[ Upstream commit 951b7ccc54591ba48755b5e0c7fc8b9623a64640 ]

015c9cbcf0ad ("mmc: sdhci-pci-gli: GL9750: Mask the replay timer timeout of
AER") added PCI_GLI_9750_CORRERR_MASK, the offset of the AER Capability in
config space, and PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT, the
Replay Timer Timeout bit in the AER Correctable Error Status register.

Use pci_find_ext_capability() to locate the AER Capability and use the
existing PCI_ERR_COR_REP_TIMER definition to mask the bit.

This removes a little bit of unnecessarily device-specific code and makes
AER-related things more greppable.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20240327214831.1544595-2-helgaas@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index fab604592acbb226d47af7d2f8780b66db07c95c..d73e34e525b816460beebc4f2f86f69a80c555d2 100644 (file)
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -27,8 +27,6 @@
 #define PCI_GLI_9750_PM_CTRL   0xFC
 #define   PCI_GLI_9750_PM_STATE          GENMASK(1, 0)
 
-#define PCI_GLI_9750_CORRERR_MASK                              0x214
-#define   PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT(12)
 
 #define SDHCI_GLI_9750_CFG2          0x848
 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
@@ -154,8 +152,6 @@
 #define PCI_GLI_9755_PM_CTRL     0xFC
 #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
 
-#define PCI_GLI_9755_CORRERR_MASK                              0x214
-#define   PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT         BIT(12)
 
 #define GLI_MAX_TUNING_LOOP 40
 
@@ -501,9 +497,7 @@ static void gl9750_hw_setting(struct sdhci_host *host)
        pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
 
        /* mask the replay timer timeout of AER */
-       pci_read_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, &value);
-       value |= PCI_GLI_9750_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
-       pci_write_config_dword(pdev, PCI_GLI_9750_CORRERR_MASK, value);
+       sdhci_gli_mask_replay_timer_timeout(pdev);
 
        gl9750_wt_off(host);
 }
@@ -715,9 +709,7 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
        pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
 
        /* mask the replay timer timeout of AER */
-       pci_read_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, &value);
-       value |= PCI_GLI_9755_CORRERR_MASK_REPLAY_TIMER_TIMEOUT;
-       pci_write_config_dword(pdev, PCI_GLI_9755_CORRERR_MASK, value);
+       sdhci_gli_mask_replay_timer_timeout(pdev);
 
        gl9755_wt_off(pdev);
 }