PCI: Move CXL DVSEC definitions into uapi/linux/pci_regs.h

The CXL DVSECs are currently defined in cxl/core/cxlpci.h. These are not
accessible to other subsystems. Move these to uapi/linux/pci_regs.h.

The CXL DVSEC definitions will be renamed and reformatted to fit better
with existing defines.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/20260114182055.46029-2-terry.bowman@amd.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>

diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h
index 1d526bea8431223e303611bdabab26680f58bab6..cdb7cf3dbcb4378d0aab4f94789eb72d37cfdc84 100644 (file)
--- a/drivers/cxl/cxlpci.h
+++ b/drivers/cxl/cxlpci.h
@@ -7,59 +7,6 @@
 
 #define CXL_MEMORY_PROGIF      0x10
 
-/*
- * See section 8.1 Configuration Space Registers in the CXL 2.0
- * Specification. Names are taken straight from the specification with "CXL" and
- * "DVSEC" redundancies removed. When obvious, abbreviations may be used.
- */
-#define PCI_DVSEC_HEADER1_LENGTH_MASK  GENMASK(31, 20)
-
-/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
-#define CXL_DVSEC_PCIE_DEVICE                                  0
-#define   CXL_DVSEC_CAP_OFFSET         0xA
-#define     CXL_DVSEC_MEM_CAPABLE      BIT(2)
-#define     CXL_DVSEC_HDM_COUNT_MASK   GENMASK(5, 4)
-#define   CXL_DVSEC_CTRL_OFFSET                0xC
-#define     CXL_DVSEC_MEM_ENABLE       BIT(2)
-#define   CXL_DVSEC_RANGE_SIZE_HIGH(i) (0x18 + (i * 0x10))
-#define   CXL_DVSEC_RANGE_SIZE_LOW(i)  (0x1C + (i * 0x10))
-#define     CXL_DVSEC_MEM_INFO_VALID   BIT(0)
-#define     CXL_DVSEC_MEM_ACTIVE       BIT(1)
-#define     CXL_DVSEC_MEM_SIZE_LOW_MASK        GENMASK(31, 28)
-#define   CXL_DVSEC_RANGE_BASE_HIGH(i) (0x20 + (i * 0x10))
-#define   CXL_DVSEC_RANGE_BASE_LOW(i)  (0x24 + (i * 0x10))
-#define     CXL_DVSEC_MEM_BASE_LOW_MASK        GENMASK(31, 28)
-
-#define CXL_DVSEC_RANGE_MAX            2
-
-/* CXL 2.0 8.1.4: Non-CXL Function Map DVSEC */
-#define CXL_DVSEC_FUNCTION_MAP                                 2
-
-/* CXL 2.0 8.1.5: CXL 2.0 Extensions DVSEC for Ports */
-#define CXL_DVSEC_PORT_EXTENSIONS                              3
-
-/* CXL 2.0 8.1.6: GPF DVSEC for CXL Port */
-#define CXL_DVSEC_PORT_GPF                                     4
-#define   CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET            0x0C
-#define     CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK           GENMASK(3, 0)
-#define     CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK          GENMASK(11, 8)
-#define   CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET            0xE
-#define     CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK           GENMASK(3, 0)
-#define     CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK          GENMASK(11, 8)
-
-/* CXL 2.0 8.1.7: GPF DVSEC for CXL Device */
-#define CXL_DVSEC_DEVICE_GPF                                   5
-
-/* CXL 2.0 8.1.8: PCIe DVSEC for Flex Bus Port */
-#define CXL_DVSEC_PCIE_FLEXBUS_PORT                            7
-
-/* CXL 2.0 8.1.9: Register Locator DVSEC */
-#define CXL_DVSEC_REG_LOCATOR                                  8
-#define   CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET                  0xC
-#define     CXL_DVSEC_REG_LOCATOR_BIR_MASK                     GENMASK(2, 0)
-#define            CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK                 GENMASK(15, 8)
-#define     CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK           GENMASK(31, 16)
-
 /*
  * NOTE: Currently all the functions which are enabled for CXL require their
  * vectors to be in the first 16.  Use this as the default max.

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 3add74ae259483bab76e7552cb28bd9c9ef0b30c..6c4b6f19b18e3de55112af066b79fa5278465906 100644 (file)
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -1253,11 +1253,6 @@
 #define PCI_DEV3_STA           0x0c    /* Device 3 Status Register */
 #define  PCI_DEV3_STA_SEGMENT  0x8     /* Segment Captured (end-to-end flit-mode detected) */
 
-/* Compute Express Link (CXL r3.1, sec 8.1.5) */
-#define PCI_DVSEC_CXL_PORT                             3
-#define PCI_DVSEC_CXL_PORT_CTL                         0x0c
-#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR              0x00000001
-
 /* Integrity and Data Encryption Extended Capability */
 #define PCI_IDE_CAP                    0x04
 #define  PCI_IDE_CAP_LINK              0x1  /* Link IDE Stream Supported */
@@ -1338,4 +1333,63 @@
 #define  PCI_IDE_SEL_ADDR_3(x)         (28 + (x) * PCI_IDE_SEL_ADDR_BLOCK_SIZE)
 #define PCI_IDE_SEL_BLOCK_SIZE(nr_assoc)  (20 + PCI_IDE_SEL_ADDR_BLOCK_SIZE * (nr_assoc))
 
+/* Compute Express Link (CXL r3.1, sec 8.1.5) */
+#define PCI_DVSEC_CXL_PORT                             3
+#define PCI_DVSEC_CXL_PORT_CTL                         0x0c
+#define PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR              0x00000001
+
+/*
+ * Compute Express Link (CXL r3.2, sec 8.1)
+ *
+ * Note that CXL DVSEC id 3 and 7 to be ignored when the CXL link state
+ * is "disconnected" (CXL r3.2, sec 9.12.3). Re-enumerate these
+ * registers on downstream link-up events.
+ */
+#define PCI_DVSEC_HEADER1_LENGTH_MASK  __GENMASK(31, 20)
+
+/* CXL 3.2 8.1.3: PCIe DVSEC for CXL Device */
+#define CXL_DVSEC_PCIE_DEVICE                          0
+#define  CXL_DVSEC_CAP_OFFSET                          0xA
+#define   CXL_DVSEC_MEM_CAPABLE                                _BITUL(2)
+#define   CXL_DVSEC_HDM_COUNT_MASK                     __GENMASK(5, 4)
+#define  CXL_DVSEC_CTRL_OFFSET                         0xC
+#define   CXL_DVSEC_MEM_ENABLE                         _BITUL(2)
+#define  CXL_DVSEC_RANGE_SIZE_HIGH(i)                  (0x18 + (i * 0x10))
+#define  CXL_DVSEC_RANGE_SIZE_LOW(i)                   (0x1C + (i * 0x10))
+#define   CXL_DVSEC_MEM_INFO_VALID                     _BITUL(0)
+#define   CXL_DVSEC_MEM_ACTIVE                         _BITUL(1)
+#define   CXL_DVSEC_MEM_SIZE_LOW_MASK                  __GENMASK(31, 28)
+#define  CXL_DVSEC_RANGE_BASE_HIGH(i)                  (0x20 + (i * 0x10))
+#define  CXL_DVSEC_RANGE_BASE_LOW(i)                   (0x24 + (i * 0x10))
+#define   CXL_DVSEC_MEM_BASE_LOW_MASK                  __GENMASK(31, 28)
+
+#define CXL_DVSEC_RANGE_MAX                            2
+
+/* CXL 3.2 8.1.4: Non-CXL Function Map DVSEC */
+#define CXL_DVSEC_FUNCTION_MAP                         2
+
+/* CXL 3.2 8.1.5: Extensions DVSEC for Ports */
+#define CXL_DVSEC_PORT                                 3
+#define   CXL_DVSEC_PORT_CTL                           0x0c
+#define    CXL_DVSEC_PORT_CTL_UNMASK_SBR               0x00000001
+
+/* CXL 3.2 8.1.6: GPF DVSEC for CXL Port */
+#define CXL_DVSEC_PORT_GPF                             4
+#define  CXL_DVSEC_PORT_GPF_PHASE_1_CONTROL_OFFSET     0x0C
+#define   CXL_DVSEC_PORT_GPF_PHASE_1_TMO_BASE_MASK     __GENMASK(3, 0)
+#define   CXL_DVSEC_PORT_GPF_PHASE_1_TMO_SCALE_MASK    __GENMASK(11, 8)
+#define  CXL_DVSEC_PORT_GPF_PHASE_2_CONTROL_OFFSET     0xE
+#define   CXL_DVSEC_PORT_GPF_PHASE_2_TMO_BASE_MASK     __GENMASK(3, 0)
+#define   CXL_DVSEC_PORT_GPF_PHASE_2_TMO_SCALE_MASK    __GENMASK(11, 8)
+
+/* CXL 3.2 8.1.7: GPF DVSEC for CXL Device */
+#define CXL_DVSEC_DEVICE_GPF                           5
+
+/* CXL 3.2 8.1.9: Register Locator DVSEC */
+#define CXL_DVSEC_REG_LOCATOR                          8
+#define  CXL_DVSEC_REG_LOCATOR_BLOCK1_OFFSET           0xC
+#define   CXL_DVSEC_REG_LOCATOR_BIR_MASK               __GENMASK(2, 0)
+#define   CXL_DVSEC_REG_LOCATOR_BLOCK_ID_MASK          __GENMASK(15, 8)
+#define   CXL_DVSEC_REG_LOCATOR_BLOCK_OFF_LOW_MASK     __GENMASK(31, 16)
+
 #endif /* LINUX_PCI_REGS_H */