arm64: dts: qcom: sm8750: Add LPASS macro codecs and pinctrl

Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm SM8750
for proper sound support.  These are fully compatible with earlier SM8550.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250312-sm8750-audio-v3-2-40fbb3e53f95@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index f75f0723e39340d748b76c96816761831e06ceda..e4670fefff7c4cc6fbdd42285276d6a870c2121d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -15,6 +15,7 @@
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,gpr.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
 
 / {
        interrupt-parent = <&intc>;
@@ -2115,6 +2116,74 @@
                        };
                };
 
+               lpass_wsa2macro: codec@6aa0000 {
+                       compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+                       reg = <0x0 0x06aa0000 0x0 0x1000>;
+                       clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&lpass_vamacro>;
+                       clock-names = "mclk",
+                                     "macro",
+                                     "dcodec",
+                                     "fsgen";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "wsa2-mclk";
+                       #sound-dai-cells = <1>;
+               };
+
+               lpass_rxmacro: codec@6ac0000 {
+                       compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
+                       reg = <0x0 0x06ac0000 0x0 0x1000>;
+                       clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&lpass_vamacro>;
+                       clock-names = "mclk",
+                                     "macro",
+                                     "dcodec",
+                                     "fsgen";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "mclk";
+                       #sound-dai-cells = <1>;
+               };
+
+               lpass_txmacro: codec@6ae0000 {
+                       compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
+                       reg = <0x0 0x06ae0000 0x0 0x1000>;
+                       clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&lpass_vamacro>;
+                       clock-names = "mclk",
+                                     "macro",
+                                     "dcodec",
+                                     "fsgen";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "mclk";
+                       #sound-dai-cells = <1>;
+               };
+
+               lpass_wsamacro: codec@6b00000 {
+                       compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
+                       reg = <0x0 0x06b00000 0x0 0x1000>;
+                       clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&lpass_vamacro>;
+                       clock-names = "mclk",
+                                     "macro",
+                                     "dcodec",
+                                     "fsgen";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "mclk";
+                       #sound-dai-cells = <1>;
+               };
+
                lpass_ag_noc: interconnect@7e40000 {
                        compatible = "qcom,sm8750-lpass-ag-noc";
                        reg = <0x0 0x07e40000 0x0 0xe080>;
@@ -2136,6 +2205,139 @@
                        #interconnect-cells = <2>;
                };
 
+               lpass_vamacro: codec@7660000 {
+                       compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
+                       reg = <0x0 0x07660000 0x0 0x2000>;
+                       clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+                       clock-names = "mclk",
+                                     "macro",
+                                     "dcodec";
+
+                       #clock-cells = <0>;
+                       clock-output-names = "fsgen";
+                       #sound-dai-cells = <1>;
+               };
+
+               lpass_tlmm: pinctrl@7760000 {
+                       compatible = "qcom,sm8750-lpass-lpi-pinctrl",
+                                    "qcom,sm8650-lpass-lpi-pinctrl";
+                       reg = <0x0 0x07760000 0x0 0x20000>;
+
+                       clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
+                                <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
+                       clock-names = "core", "audio";
+
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&lpass_tlmm 0 0 23>;
+
+                       tx_swr_active: tx-swr-active-state {
+                               clk-pins {
+                                       pins = "gpio0";
+                                       function = "swr_tx_clk";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-disable;
+                               };
+
+                               data-pins {
+                                       pins = "gpio1", "gpio2", "gpio14";
+                                       function = "swr_tx_data";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-bus-hold;
+                               };
+                       };
+
+                       rx_swr_active: rx-swr-active-state {
+                               clk-pins {
+                                       pins = "gpio3";
+                                       function = "swr_rx_clk";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-disable;
+                               };
+
+                               data-pins {
+                                       pins = "gpio4", "gpio5";
+                                       function = "swr_rx_data";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-bus-hold;
+                               };
+                       };
+
+                       dmic01_default: dmic01-default-state {
+                               clk-pins {
+                                       pins = "gpio6";
+                                       function = "dmic1_clk";
+                                       drive-strength = <8>;
+                                       output-high;
+                               };
+
+                               data-pins {
+                                       pins = "gpio7";
+                                       function = "dmic1_data";
+                                       drive-strength = <8>;
+                                       input-enable;
+                               };
+                       };
+
+                       dmic23_default: dmic23-default-state {
+                               clk-pins {
+                                       pins = "gpio8";
+                                       function = "dmic2_clk";
+                                       drive-strength = <8>;
+                                       output-high;
+                               };
+
+                               data-pins {
+                                       pins = "gpio9";
+                                       function = "dmic2_data";
+                                       drive-strength = <8>;
+                                       input-enable;
+                               };
+                       };
+
+                       wsa_swr_active: wsa-swr-active-state {
+                               clk-pins {
+                                       pins = "gpio10";
+                                       function = "wsa_swr_clk";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-disable;
+                               };
+
+                               data-pins {
+                                       pins = "gpio11";
+                                       function = "wsa_swr_data";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-bus-hold;
+                               };
+                       };
+
+                       wsa2_swr_active: wsa2-swr-active-state {
+                               clk-pins {
+                                       pins = "gpio15";
+                                       function = "wsa2_swr_clk";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-disable;
+                               };
+
+                               data-pins {
+                                       pins = "gpio16";
+                                       function = "wsa2_swr_data";
+                                       drive-strength = <2>;
+                                       slew-rate = <1>;
+                                       bias-bus-hold;
+                               };
+                       };
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8750-pdc", "qcom,pdc";
                        reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>;