]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/amdkfd: Fix VGPR bank state save in gfx12.1 trap handler
authorJay Cornwall <jay.cornwall@amd.com>
Thu, 23 Oct 2025 20:28:39 +0000 (15:28 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 5 Jan 2026 21:59:56 +0000 (16:59 -0500)
S_SETREG_IMM32_B32 does not apply a mask to the MODE bank bits.
SRC2 is consequently unconditonally cleared during context save.

Use S_SETREG_B32 instead to preserve SRC2.

Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>
Reviewed-by: Lancelot Six <lancelot.six@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h
drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx12.asm

index 5c6d533a595620757f4fc8a62e64a861571577e9..d82ce2f1e9b9221bf4f6fb6db291a04b3ae543ac 100644 (file)
@@ -4731,7 +4731,7 @@ static const uint32_t cwsr_trap_gfx12_1_0_hex[] = {
        0xb8eff822, 0xb980f822,
        0x00000000, 0xb8fa2b01,
        0x847a997a, 0x8c6d7a6d,
-       0xb9802b01, 0x00000000,
+       0xbefa0080, 0xb97a2b01,
        0xbefa007e, 0x8b7bff7f,
        0x01ffffff, 0xbefe00c1,
        0xbeff00c1, 0xee0a407a,
index a807e7557e93fd0f14bc2b370f71f176fc76bb58..d59400d242d1952892988469ebf9d40e5178eb07 100644 (file)
@@ -414,7 +414,8 @@ L_HAVE_VGPRS:
        s_getreg_b32    s_save_tmp, hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE)
        s_lshl_b32      s_save_tmp, s_save_tmp, S_SAVE_PC_HI_DST_SRC0_SRC1_VGPR_MSB_SHIFT
        s_or_b32        s_save_pc_hi, s_save_pc_hi, s_save_tmp
-       s_setreg_imm32_b32      hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), 0
+       s_mov_b32       s_save_tmp, 0
+       s_setreg_b32    hwreg(HW_REG_WAVE_MODE, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SHIFT, SQ_WAVE_MODE_DST_SRC0_SRC1_VGPR_MSB_SIZE), s_save_tmp
 #endif
 
        // Trap temporaries must be saved via VGPR but all VGPRs are in use.