coresight: Change syncfreq to be a u8

TRCSYNCPR.PERIOD is the only functional part of TRCSYNCPR and it only
has 5 valid bits so it can be stored in a u8.

Reviewed-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Tested-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20251128-james-cs-syncfreq-v8-1-4d319764cc58@linaro.org

diff --git a/drivers/hwtracing/coresight/coresight-etm4x.h b/drivers/hwtracing/coresight/coresight-etm4x.h
index 012c52fd19338133129752d35523dc102df24604..0287d19ce12ed9e1523983c9a2d3314daca6d200 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x.h
+++ b/drivers/hwtracing/coresight/coresight-etm4x.h
@@ -825,7 +825,6 @@ struct etmv4_config {
        u32                             eventctrl1;
        u32                             stall_ctrl;
        u32                             ts_ctrl;
-       u32                             syncfreq;
        u32                             ccctlr;
        u32                             bb_ctrl;
        u32                             vinst_ctrl;
@@ -833,6 +832,7 @@ struct etmv4_config {
        u32                             vissctlr;
        u32                             vipcssctlr;
        u8                              seq_idx;
+       u8                              syncfreq;
        u32                             seq_ctrl[ETM_MAX_SEQ_STATES];
        u32                             seq_rst;
        u32                             seq_state;