return True;
}
+ /* -------------------- BRK -------------------- */
+ /* 31 23 20 4
+ 1101 0100 001 imm16 00000 BRK #imm16
+ */
+ if (INSN(31,24) == BITS8(1,1,0,1,0,1,0,0)
+ && INSN(23,21) == BITS3(0,0,1) && INSN(4,0) == BITS5(0,0,0,0,0)) {
+ UInt imm16 = INSN(20,5);
+ /* Request SIGTRAP and then restart of this insn. */
+ putPC(mkU64(guest_PC_curr_instr + 0));
+ dres->whatNext = Dis_StopHere;
+ dres->jk_StopHere = Ijk_SigTRAP;
+ DIP("brk #%u\n", imm16);
+ return True;
+ }
+
//fail:
vex_printf("ARM64 front end: branch_etc\n");
return False;
case Ijk_InvalICache: trcval = VEX_TRC_JMP_INVALICACHE; break;
case Ijk_FlushDCache: trcval = VEX_TRC_JMP_FLUSHDCACHE; break;
case Ijk_NoRedir: trcval = VEX_TRC_JMP_NOREDIR; break;
- //case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
+ case Ijk_SigTRAP: trcval = VEX_TRC_JMP_SIGTRAP; break;
//case Ijk_SigSEGV: trcval = VEX_TRC_JMP_SIGSEGV; break;
case Ijk_Boring: trcval = VEX_TRC_JMP_BORING; break;
/* We don't expect to see the following being assisted. */