As the watchdog is normally on the same bus as the UART peripheral, the
bootloader will have ensured the bus' clock is up and running before the
watchdog driver is probed. Nevertheless, let's do things the right way
and enable the watchdog's clock before performing I/O accesses.
Signed-off-by: Sander Vanheule <sander@svanheule.net>
Link: https://lore.kernel.org/r/20260515212351.752054-3-sander@svanheule.net
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
if (IS_ERR(ctrl->base))
return PTR_ERR(ctrl->base);
+ ret = otto_wdt_probe_clk(ctrl);
+ if (ret)
+ return ret;
+
/* Clear any old interrupts and reset initial state */
iowrite32(OTTO_WDT_INTR_PHASE_1 | OTTO_WDT_INTR_PHASE_2,
ctrl->base + OTTO_WDT_REG_INTR);
iowrite32(OTTO_WDT_CTRL_DEFAULT, ctrl->base + OTTO_WDT_REG_CTRL);
- ret = otto_wdt_probe_clk(ctrl);
- if (ret)
- return ret;
-
ctrl->irq_phase1 = platform_get_irq_byname(pdev, "phase1");
if (ctrl->irq_phase1 < 0)
return ctrl->irq_phase1;