struct drm_crtc base;
struct drm_plane primary;
- const struct tilcdc_panel_info *info;
struct drm_pending_vblank_event *event;
struct mutex enable_lock;
bool enabled;
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
struct drm_device *dev = crtc->dev;
struct tilcdc_drm_private *priv = dev->dev_private;
- const struct tilcdc_panel_info *info = tilcdc_crtc->info;
uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
struct drm_display_mode *mode = &crtc->state->adjusted_mode;
struct drm_framebuffer *fb = crtc->primary->state->fb;
- if (WARN_ON(!info))
- return;
-
if (WARN_ON(!fb))
return;
reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
/* Use 16 bit DMA burst size by default */
reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
+
if (priv->fifo_th) {
int fifo_th_val = ilog2(priv->fifo_th) - 3;
reg |= (fifo_th_val << 8);
- } else {
- reg |= (info->fifo_th << 8);
}
tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
0x000ff000 /* Palette Loading Delay bits */);
reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
- if (info->tft_alt_mode)
- reg |= LCDC_TFT_ALT_ENABLE;
if (priv->rev == 2) {
switch (fb->format->format) {
case DRM_FORMAT_BGR565:
reg |= 128 << 12;
tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
- if (info->invert_pxl_clk ||
- mode->flags == DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
+ if (mode->flags == DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
else
tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
- if (info->sync_edge ||
- mode->flags == DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE)
+ if (mode->flags == DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE)
tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
else
tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
else
tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
- if (info->raster_order)
- tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
- else
- tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
-
tilcdc_crtc_set_clk(crtc);
tilcdc_crtc_load_palette(crtc);
.atomic_flush = tilcdc_crtc_atomic_flush,
};
-void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
- const struct tilcdc_panel_info *info)
-{
- struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
- tilcdc_crtc->info = info;
-}
-
void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
const struct tilcdc_module_ops *funcs);
void tilcdc_module_cleanup(struct tilcdc_module *mod);
-/* Panel config that needs to be set in the crtc, but is not coming from
- * the mode timings. The display module is expected to call
- * tilcdc_crtc_set_panel_info() to set this during modeset.
- */
-struct tilcdc_panel_info {
-
- /* AC Bias Pin Frequency */
- uint32_t ac_bias;
-
- /* AC Bias Pin Transitions per Interrupt */
- uint32_t ac_bias_intrpt;
-
- /* DMA burst size */
- uint32_t dma_burst_sz;
-
- /* Bits per pixel */
- uint32_t bpp;
-
- /* FIFO DMA Request Delay */
- uint32_t fdd;
-
- /* TFT Alternative Signal Mapping (Only for active) */
- bool tft_alt_mode;
-
- /* Invert pixel clock */
- bool invert_pxl_clk;
-
- /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
- uint32_t sync_edge;
-
- /* Horizontal and Vertical Sync: Control: 0=ignore */
- uint32_t sync_ctrl;
-
- /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
- uint32_t raster_order;
-
- /* DMA FIFO threshold */
- uint32_t fifo_th;
-};
-
#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
int tilcdc_crtc_create(struct drm_device *dev);
irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
-void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
- const struct tilcdc_panel_info *info);
void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
void tilcdc_crtc_destroy(struct drm_crtc *crtc);
int tilcdc_crtc_update_fb(struct drm_crtc *crtc,