]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
drm/i915/psr: Move sink_sync_latency to intel_connector
authorJouni Högander <jouni.hogander@intel.com>
Thu, 4 Dec 2025 10:47:33 +0000 (12:47 +0200)
committerJouni Högander <jouni.hogander@intel.com>
Mon, 8 Dec 2025 06:16:03 +0000 (08:16 +0200)
As everything else related to PSR and Panel Replay capabilities are moved
into intel_connector move sink_sync_latency as well.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Imre Deak <imre.deak@intel.com>
Link: https://patch.msgid.link/20251204104733.1106145-9-jouni.hogander@intel.com
drivers/gpu/drm/i915/display/intel_display_types.h
drivers/gpu/drm/i915/display/intel_psr.c

index 3e728fe10ae896925e3a0ea4d4c9eedbb270f8e1..6ff53cd580525a61effd36c7f86c6defea0feba1 100644 (file)
@@ -588,6 +588,8 @@ struct intel_connector {
 
                        u16 su_w_granularity;
                        u16 su_y_granularity;
+
+                       u8 sync_latency;
                } psr_caps;
        } dp;
 
@@ -1746,7 +1748,6 @@ struct intel_psr {
        bool psr2_sel_fetch_cff_enabled;
        bool su_region_et_enabled;
        bool req_psr2_sdp_prior_scanline;
-       u8 sink_sync_latency;
        ktime_t last_entry_attempt;
        ktime_t last_exit;
        bool sink_not_reliable;
index 515eac6fd3556742ff5bdd1be9f703d4ba4b58af..2a378a5adc5996ca0cb6480a61f6ad066675610f 100644 (file)
@@ -684,8 +684,7 @@ static void _psr_init_dpcd(struct intel_dp *intel_dp, struct intel_connector *co
        connector->dp.psr_caps.support = true;
        intel_dp->psr.sink_support = true;
 
-       intel_dp->psr.sink_sync_latency =
-               intel_dp_get_sink_sync_latency(intel_dp);
+       connector->dp.psr_caps.sync_latency = intel_dp_get_sink_sync_latency(intel_dp);
 
        if (DISPLAY_VER(display) >= 9 &&
            connector->dp.psr_caps.dpcd[0] >= DP_PSR2_WITH_Y_COORD_IS_SUPPORTED) {
@@ -910,7 +909,7 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp)
         * off-by-one issue that HW has in some cases.
         */
        idle_frames = max(6, connector->panel.vbt.psr.idle_frames);
-       idle_frames = max(idle_frames, intel_dp->psr.sink_sync_latency + 1);
+       idle_frames = max(idle_frames, connector->dp.psr_caps.sync_latency + 1);
 
        if (drm_WARN_ON(display->drm, idle_frames > 0xf))
                idle_frames = 0xf;
@@ -1005,10 +1004,11 @@ static int psr2_block_count(struct intel_dp *intel_dp)
 
 static u8 frames_before_su_entry(struct intel_dp *intel_dp)
 {
+       struct intel_connector *connector = intel_dp->attached_connector;
        u8 frames_before_su_entry;
 
        frames_before_su_entry = max_t(u8,
-                                      intel_dp->psr.sink_sync_latency + 1,
+                                      connector->dp.psr_caps.sync_latency + 1,
                                       2);
 
        /* Entry setup frames must be at least 1 less than frames before SU entry */