coresight: etm4x: Extract the trace unit controlling

[ Upstream commit 40f682ae5086366d51e29e66eb8a344501245d0d ]

The trace unit is controlled in the ETM hardware enabling and disabling.
The sequential changes for support AUX pause and resume will reuse the
same operations.

Extract the operations in the etm4_{enable|disable}_trace_unit()
functions.  A minor improvement in etm4_enable_trace_unit() is for
returning the timeout error to callers.

Signed-off-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Link: https://lore.kernel.org/r/20250401180708.385396-2-leo.yan@arm.com
Stable-dep-of: 64eb04ae5452 ("coresight: etm4x: Add context synchronization before enabling trace")
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 9164e134814ae0e71441691c3bfa1fbfbac961b8..853a170439608fa62b6ca562aa4ef2030ef91c56 100644 (file)
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -422,6 +422,44 @@ static int etm4x_wait_status(struct csdev_access *csa, int pos, int val)
        return coresight_timeout(csa, TRCSTATR, pos, val);
 }
 
+static int etm4_enable_trace_unit(struct etmv4_drvdata *drvdata)
+{
+       struct coresight_device *csdev = drvdata->csdev;
+       struct device *etm_dev = &csdev->dev;
+       struct csdev_access *csa = &csdev->access;
+
+       /*
+        * ETE mandates that the TRCRSR is written to before
+        * enabling it.
+        */
+       if (etm4x_is_ete(drvdata))
+               etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
+
+       etm4x_allow_trace(drvdata);
+       /* Enable the trace unit */
+       etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
+
+       /* Synchronize the register updates for sysreg access */
+       if (!csa->io_mem)
+               isb();
+
+       /* wait for TRCSTATR.IDLE to go back down to '0' */
+       if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0)) {
+               dev_err(etm_dev,
+                       "timeout while waiting for Idle Trace Status\n");
+               return -ETIME;
+       }
+
+       /*
+        * As recommended by section 4.3.7 ("Synchronization when using the
+        * memory-mapped interface") of ARM IHI 0064D
+        */
+       dsb(sy);
+       isb();
+
+       return 0;
+}
+
 static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
 {
        int i, rc;
@@ -531,33 +569,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
                etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR);
        }
 
-       /*
-        * ETE mandates that the TRCRSR is written to before
-        * enabling it.
-        */
-       if (etm4x_is_ete(drvdata))
-               etm4x_relaxed_write32(csa, TRCRSR_TA, TRCRSR);
-
-       etm4x_allow_trace(drvdata);
-       /* Enable the trace unit */
-       etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
-
-       /* Synchronize the register updates for sysreg access */
-       if (!csa->io_mem)
-               isb();
-
-       /* wait for TRCSTATR.IDLE to go back down to '0' */
-       if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 0))
-               dev_err(etm_dev,
-                       "timeout while waiting for Idle Trace Status\n");
-
-       /*
-        * As recommended by section 4.3.7 ("Synchronization when using the
-        * memory-mapped interface") of ARM IHI 0064D
-        */
-       dsb(sy);
-       isb();
-
+       rc = etm4_enable_trace_unit(drvdata);
 done:
        etm4_cs_lock(drvdata, csa);
 
@@ -889,25 +901,12 @@ static int etm4_enable(struct coresight_device *csdev, struct perf_event *event,
        return ret;
 }
 
-static void etm4_disable_hw(void *info)
+static void etm4_disable_trace_unit(struct etmv4_drvdata *drvdata)
 {
        u32 control;
-       struct etmv4_drvdata *drvdata = info;
-       struct etmv4_config *config = &drvdata->config;
        struct coresight_device *csdev = drvdata->csdev;
        struct device *etm_dev = &csdev->dev;
        struct csdev_access *csa = &csdev->access;
-       int i;
-
-       etm4_cs_unlock(drvdata, csa);
-       etm4_disable_arch_specific(drvdata);
-
-       if (!drvdata->skip_power_up) {
-               /* power can be removed from the trace unit now */
-               control = etm4x_relaxed_read32(csa, TRCPDCR);
-               control &= ~TRCPDCR_PU;
-               etm4x_relaxed_write32(csa, control, TRCPDCR);
-       }
 
        control = etm4x_relaxed_read32(csa, TRCPRGCTLR);
 
@@ -948,6 +947,28 @@ static void etm4_disable_hw(void *info)
         * of ARM IHI 0064H.b.
         */
        isb();
+}
+
+static void etm4_disable_hw(void *info)
+{
+       u32 control;
+       struct etmv4_drvdata *drvdata = info;
+       struct etmv4_config *config = &drvdata->config;
+       struct coresight_device *csdev = drvdata->csdev;
+       struct csdev_access *csa = &csdev->access;
+       int i;
+
+       etm4_cs_unlock(drvdata, csa);
+       etm4_disable_arch_specific(drvdata);
+
+       if (!drvdata->skip_power_up) {
+               /* power can be removed from the trace unit now */
+               control = etm4x_relaxed_read32(csa, TRCPDCR);
+               control &= ~TRCPDCR_PU;
+               etm4x_relaxed_write32(csa, control, TRCPDCR);
+       }
+
+       etm4_disable_trace_unit(drvdata);
 
        /* read the status of the single shot comparators */
        for (i = 0; i < drvdata->nr_ss_cmp; i++) {