drm/amd/display: Consolidate dmub fb info to a single struct

[WHY&HOW]
Consolidate dmub fb info into a single structure to simplify translation
between components.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Dillon Varone <Dillon.Varone@amd.com>
Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index b7e00e49c2250f0ff3a6a926727c5020d5a7f542..ccb45fb37f8d0ee725ab4b1c8f5d538103c876c6 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1336,8 +1336,8 @@ static int dm_dmub_hw_init(struct amdgpu_device *adev)
 
        /* Initialize hardware. */
        memset(&hw_params, 0, sizeof(hw_params));
-       hw_params.fb_base = adev->gmc.fb_start;
-       hw_params.fb_offset = adev->vm_manager.vram_base_offset;
+       hw_params.soc_fb_info.fb_base = adev->gmc.fb_start;
+       hw_params.soc_fb_info.fb_offset = adev->vm_manager.vram_base_offset;
 
        /* backdoor load firmware and trigger dmub running */
        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)

diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
index 12c1f9f7115a5e51107ddb53a786b9a55767a2b8..3b6bba0170406ca3638f279e1aa247b654198630 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
+++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h
@@ -307,6 +307,16 @@ struct dmub_srv_fb_info {
        struct dmub_fb fb[DMUB_WINDOW_TOTAL];
 };
 
+/**
+ * struct dmub_soc_fb_info - relevant addresses from the frame buffer
+ * @fb_base: base of the framebuffer aperture
+ * @fb_offset: offset of the framebuffer aperture
+ */
+struct dmub_soc_fb_info {
+       uint64_t fb_base;
+       uint64_t fb_offset;
+};
+
 /*
  * struct dmub_srv_hw_params - params for dmub hardware initialization
  * @fb: framebuffer info for each region
@@ -317,8 +327,7 @@ struct dmub_srv_fb_info {
  */
 struct dmub_srv_hw_params {
        struct dmub_fb *fb[DMUB_WINDOW_TOTAL];
-       uint64_t fb_base;
-       uint64_t fb_offset;
+       struct dmub_soc_fb_info soc_fb_info;
        uint32_t psp_version;
        bool load_inst_const;
        bool skip_panel_power_sequence;
@@ -610,8 +619,7 @@ struct dmub_srv {
        bool hw_init;
        bool dpia_supported;
 
-       uint64_t fb_base;
-       uint64_t fb_offset;
+       struct dmub_soc_fb_info soc_fb_info;
        uint32_t psp_version;
 
        /* Feature capabilities reported by fw */

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
index 73888c1bea935aa1f81ec9188331ab723d3e7e99..54df2147e4dcf03b387eb93a49c1526fb2f11fad 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.c
@@ -63,9 +63,9 @@ static void dmub_dcn20_get_fb_base_offset(struct dmub_srv *dmub,
 {
        uint32_t tmp;
 
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
index a4abe951c8382efa58c569a9a5661c7caa0cfd04..84a6eb3f677deb49b4ecc288c11265720ad67582 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn30.c
@@ -63,9 +63,9 @@ static void dmub_dcn30_get_fb_base_offset(struct dmub_srv *dmub,
 {
        uint32_t tmp;
 
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
index cd04d7c756c3da1c40a90a8d37e2299dcca32545..a0cefc03b21dab6bbb6b07bee71f9711c6c7c2eb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn31.c
@@ -59,9 +59,9 @@ static void dmub_dcn31_get_fb_base_offset(struct dmub_srv *dmub,
 {
        uint32_t tmp;
 
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
index 7e9856289910840e8c0d3e8a48a46b276ac8d826..2f99a2772599e2b7b7bf9b023c6ac5f343ecf0b4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn32.c
@@ -65,9 +65,9 @@ static void dmub_dcn32_get_fb_base_offset(struct dmub_srv *dmub,
 {
        uint32_t tmp;
 
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
index e13557ed97be532bf75108c6701f9de407c4154c..6a2d35756c8ca969fa787761705e626b9e0555b7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c
@@ -63,9 +63,9 @@ static void dmub_dcn35_get_fb_base_offset(struct dmub_srv *dmub,
        uint32_t tmp;
 
        /*
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
        */

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
index 95542299e3b38367ba1f36c3459d1b797f23a6c3..16ed07f0e96d7590ffd9c9fffce8f3f599fba81f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn401.c
@@ -39,9 +39,9 @@ static void dmub_dcn401_get_fb_base_offset(struct dmub_srv *dmub,
 {
        uint32_t tmp;
 
-       if (dmub->fb_base || dmub->fb_offset) {
-               *fb_base = dmub->fb_base;
-               *fb_offset = dmub->fb_offset;
+       if (dmub->soc_fb_info.fb_base || dmub->soc_fb_info.fb_offset) {
+               *fb_base = dmub->soc_fb_info.fb_base;
+               *fb_offset = dmub->soc_fb_info.fb_offset;
                return;
        }
 

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index be893531ae7da83a0c29a480c824b37cc8371156..019eb005bba803937687b0bfcce11e15db3c6372 100644 (file)
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -709,8 +709,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
                }
        }
 
-       dmub->fb_base = params->fb_base;
-       dmub->fb_offset = params->fb_offset;
+       memcpy(&dmub->soc_fb_info, &params->soc_fb_info, sizeof(params->soc_fb_info));
        dmub->psp_version = params->psp_version;
 
        if (dmub->hw_funcs.reset)