arm64: dts: renesas: r8a77951: Describe PCIe root ports

Add nodes which describe the root ports in the PCIe controller DT nodes.
This can be used together with the pwrctrl driver to control clock and
power supply to a PCIe slot.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/20260118135038.8033-2-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 607f62a448d89206f933157aaecbcdd9eaa5d5a4..59a0f2e1479d0898d522111b0f6be8b19bcd9d0b 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -2814,6 +2814,16 @@
                        iommu-map = <0 &ipmmu_hc 0 1>;
                        iommu-map-mask = <0>;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec0_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                pciec1: pcie@ee800000 {
@@ -2843,6 +2853,16 @@
                        iommu-map = <0 &ipmmu_hc 1 1>;
                        iommu-map-mask = <0>;
                        status = "disabled";
+
+                       /* PCIe bridge, Root Port */
+                       pciec1_rp: pci@0,0 {
+                               #address-cells = <3>;
+                               #size-cells = <2>;
+                               reg = <0x0 0x0 0x0 0x0 0x0>;
+                               compatible = "pciclass,0604";
+                               device_type = "pci";
+                               ranges;
+                       };
                };
 
                pciec0_ep: pcie-ep@fe000000 {