perf/x86/intel: Disable PMI for self-reloaded ACR events

On platforms with Auto Counter Reload (ACR) support, such as NVL, a
"NMI received for unknown reason 30" warning is observed when running
multiple events in a group with ACR enabled:

  $ perf record -e '{instructions/period=20000,acr_mask=0x2/u,\
    cycles/period=40000,acr_mask=0x3/u}' ./test

The warning occurs because the Performance Monitoring Interrupt (PMI)
is enabled for the self-reloaded event (the cycles event in this case).
According to the Intel SDM, the overflow bit
(IA32_PERF_GLOBAL_STATUS.PMCn_OVF) is never set for self-reloaded events.
Since the bit is not set, the perf NMI handler cannot identify the source
of the interrupt, leading to the "unknown reason" message.

Furthermore, enabling PMI for self-reloaded events is unnecessary and
can lead to extraneous records that pollute the user's requested data.

Disable the interrupt bit for all events configured with ACR self-reload.

Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
Reported-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://patch.msgid.link/20260430002558.712334-4-dapeng1.mi@linux.intel.com

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index f8deb67b3c51131ed740eb616010e2c3ac646b81..ead6d95cec6a015f4e4a139138133884b3d3fc4a 100644 (file)
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3118,11 +3118,11 @@ static void intel_pmu_enable_fixed(struct perf_event *event)
        intel_set_masks(event, idx);
 
        /*
-        * Enable IRQ generation (0x8), if not PEBS,
-        * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
-        * if requested:
+        * Enable IRQ generation (0x8), if not PEBS or self-reloaded
+        * ACR event, and enable ring-3 counting (0x2) and ring-0
+        * counting (0x1) if requested:
         */
-       if (!event->attr.precise_ip)
+       if (!event->attr.precise_ip && !is_acr_self_reload_event(event))
                bits |= INTEL_FIXED_0_ENABLE_PMI;
        if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
                bits |= INTEL_FIXED_0_USER;
@@ -3306,6 +3306,15 @@ static void intel_pmu_enable_event(struct perf_event *event)
                intel_set_masks(event, idx);
                static_call_cond(intel_pmu_enable_acr_event)(event);
                static_call_cond(intel_pmu_enable_event_ext)(event);
+               /*
+                * For self-reloaded ACR event, don't enable PMI since
+                * HW won't set overflow bit in GLOBAL_STATUS. Otherwise,
+                * the PMI would be recognized as a suspicious NMI.
+                */
+               if (is_acr_self_reload_event(event))
+                       hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
+               else if (!event->attr.precise_ip)
+                       hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
                __x86_pmu_enable_event(hwc, enable_mask);
                break;
        case INTEL_PMC_IDX_FIXED ... INTEL_PMC_IDX_FIXED_BTS - 1:

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index fad87d3c8b2caa34a539cdf2570409d5abf8e3b0..524668dcf4cc10bb2efd61249b8d137e8dd37104 100644 (file)
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -137,6 +137,16 @@ static inline bool is_acr_event_group(struct perf_event *event)
        return check_leader_group(event->group_leader, PERF_X86_EVENT_ACR);
 }
 
+static inline bool is_acr_self_reload_event(struct perf_event *event)
+{
+       struct hw_perf_event *hwc = &event->hw;
+
+       if (hwc->idx < 0)
+               return false;
+
+       return test_bit(hwc->idx, (unsigned long *)&hwc->config1);
+}
+
 struct amd_nb {
        int nb_id;  /* NorthBridge id */
        int refcnt; /* reference count */