RISC-V: Fix vsetvl pass ICE

This patch fix pr111234 (a vsetvl pass ICE) when fuse a mask any
vlmax vsetvl_vtype_change_only insn with a mu vsetvl insn.

	PR target/111234

gcc/ChangeLog:

	* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Remove condition.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/vsetvl/pr111234.c: New test.

(cherry picked from commit ac55f9710fe82a4ed8cb132f57303775ce60e5d1)

diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index 36d2e6e6f20398be5aba2488ca9ff602ad3b5796..587c6975a709f957c459b2f5d03bf33d30d8e7c1 100644 (file)
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -649,7 +649,7 @@ gen_vsetvl_pat (rtx_insn *rinsn, const vector_insn_info &info,
       && fault_first_load_p (info.get_insn ()->rtl ()))
     new_info.set_avl_info (
       avl_info (get_avl (info.get_insn ()->rtl ()), nullptr));
-  if (vsetvl_insn_p (rinsn) || vlmax_avl_p (info.get_avl ()))
+  if (vsetvl_insn_p (rinsn))
     {
       rtx dest = get_vl (rinsn);
       new_pat = gen_vsetvl_pat (VSETVL_NORMAL, new_info, vl ? vl : dest);

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
new file mode 100644 (file)
index 0000000..ee5eec4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111234.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */
+
+#include <riscv_vector.h>
+
+void
+f (vint32m1_t *in, vint64m2_t *out, vbool32_t *m, int b)
+{
+  vint32m1_t va = *in;
+  vbool32_t mask = *m;
+  vint64m2_t vb
+    = __riscv_vwadd_vx_i64m2_m (mask, va, 1, __riscv_vsetvlmax_e64m2 ());
+  vint64m2_t vc = __riscv_vadd_vx_i64m2 (vb, 1, __riscv_vsetvlmax_e64m2 ());
+
+  if (b != 0)
+    vc = __riscv_vadd_vx_i64m2_mu (mask, vc, vc, 1, __riscv_vsetvlmax_e64m2 ());
+
+  *out = vc;
+}