clk: rockchip: rk3568: Add PLL rate for 132MHz

Add PLL rate for 132 MHz to allow raydium-rm67200 panel with
1080x1920 resolution to run at 60 fps that driven by VPLL.

Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Link: https://lore.kernel.org/r/20250615123922.661998-1-andyshrk@163.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index d48ab9d6c064632498a1f7eaff22952e8e62b642..97d279399ae84ac1b63ddf0d65cd23deeed7d07f 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(200000000, 1, 100, 3, 4, 1, 0),
        RK3036_PLL_RATE(148500000, 1, 99, 4, 4, 1, 0),
        RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
+       RK3036_PLL_RATE(132000000, 1, 66, 6, 2, 1, 0),
        RK3036_PLL_RATE(128000000, 1, 16, 3, 1, 1, 0),
        RK3036_PLL_RATE(126400000, 1, 79, 5, 3, 1, 0),
        RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),