Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians...

This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.

DDR and memory handling

  * Add DRAM size checking support for Arria10.
  * Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
  * Assign unit address to memory node for improved memory
    representation and consistency.

Agilex / Agilex5 updates

  * Restore multi-DTB support for NAND boot and fix NAND clock handling.
  * Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
  * Fix DT property naming conventions for Agilex5.
  * Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
    to avoid unintended clock control.

New board support

  * Add support for CoreCourse Cyclone V boards:
     * AC501
     * AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.

Fixes and cleanup

  * Fix GEN5 handoff script path.
  * Remove incorrect CONFIG_SPL_LDSCRIPT settings.
  * Replace legacy TARGET namespace and perform related cleanup across
    SoCFPGA code.
  * General Kconfig, build and SoCFPGA maintenance updates.

Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.

[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added]
Signed-off-by: Tom Rini <trini@konsulko.com>

diff --cc arch/arm/mach-socfpga/Kconfig
index f2e959b5662464d70b1e7080009718341c6d2cf4,3a9e018ce2342676a180b4335306a204c4290d7a..aec0fb7b1c8e3d36680b94b775d9611588194192
--- 1/arch/arm/mach-socfpga/Kconfig
--- 2/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@@ -237,7 -237,15 +237,15 @@@ config TARGET_SOCFPGA_TERASIC_DE1_SO
  
  config TARGET_SOCFPGA_TERASIC_SOCKIT
        bool "Terasic SoCkit (Cyclone V)"
-       select TARGET_SOCFPGA_CYCLONE5
+       select ARCH_SOCFPGA_CYCLONE5
+ 
+ config TARGET_SOCFPGA_CORECOURSE_AC501SOC
+       bool "CoreCourse AC501SoC (Cyclone V)"
 -      select TARGET_SOCFPGA_CYCLONE5
++      select ARCH_SOCFPGA_CYCLONE5
+ 
+ config TARGET_SOCFPGA_CORECOURSE_AC550SOC
+       bool "CoreCourse AC550SoC (Cyclone V)"
 -      select TARGET_SOCFPGA_CYCLONE5
++      select ARCH_SOCFPGA_CYCLONE5
  
  endchoice