drm/amd/pm: fix pp_dpm_pcie wrong state issue for smu v13.0.7

put wrong value into incorrect data into following function,
which caused it to fail to match the correct item on smu v13.0.7:
smu_cmn_print_pcie_levels()

Fixes: b2debbbb60f1 ("drm/amd/pm: Use common helper for smuv13.0.7 dpm")
Signed-off-by: Yang Wang <kevinyang.wang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 1465e0c80175098ebb96665936ed84010187b22b..b60c7ff75a64b8156d06b76eef88313a48374edb 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1223,8 +1223,10 @@ static int smu_v13_0_7_emit_clk_levels(struct smu_context *smu,
                        return ret;
 
                pcie_table = &(dpm_context->dpm_tables.pcie_table);
-               return smu_cmn_print_pcie_levels(smu, pcie_table, gen_speed,
-                                                lane_width, buf, offset);
+               return smu_cmn_print_pcie_levels(smu, pcie_table,
+                                                SMU_DPM_PCIE_GEN_IDX(gen_speed),
+                                                SMU_DPM_PCIE_WIDTH_IDX(lane_width),
+                                                buf, offset);
        case SMU_OD_SCLK:
                if (!smu_v13_0_7_is_od_feature_supported(smu,
                                                         PP_OD_FEATURE_GFXCLK_BIT))