#define LYNX_28G_NUM_PLL 2
/* General registers per SerDes block */
-#define LYNX_28G_PCC8 0x10a0
-#define LYNX_28G_PCC8_SGMII 0x1
-#define LYNX_28G_PCC8_SGMII_DIS 0x0
+#define PCC8 0x10a0
+#define PCC8_SGMII 0x1
+#define PCC8_SGMII_DIS 0x0
-#define LYNX_28G_PCCC 0x10b0
-#define LYNX_28G_PCCC_10GBASER 0x9
-#define LYNX_28G_PCCC_USXGMII 0x1
-#define LYNX_28G_PCCC_SXGMII_DIS 0x0
+#define PCCC 0x10b0
+#define PCCC_10GBASER 0x9
+#define PCCC_USXGMII 0x1
+#define PCCC_SXGMII_DIS 0x0
-#define LYNX_28G_LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
+#define LNa_PCC_OFFSET(lane) (4 * (LYNX_28G_NUM_LANE - (lane->id) - 1))
/* Per PLL registers */
-#define LYNX_28G_PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
-#define LYNX_28G_PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
-#define LYNX_28G_PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
-
-#define LYNX_28G_PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
-#define LYNX_28G_PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_100MHZ 0x0
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_125MHZ 0x10000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_156MHZ 0x20000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_150MHZ 0x30000
-#define LYNX_28G_PLLnCR0_REFCLK_SEL_161MHZ 0x40000
-
-#define LYNX_28G_PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
-#define LYNX_28G_PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
-#define LYNX_28G_PLLnCR1_FRATE_5G_10GVCO 0x0
-#define LYNX_28G_PLLnCR1_FRATE_5G_25GVCO 0x10000000
-#define LYNX_28G_PLLnCR1_FRATE_10G_20GVCO 0x6000000
+#define PLLnRSTCTL(pll) (0x400 + (pll) * 0x100 + 0x0)
+#define PLLnRSTCTL_DIS(rstctl) (((rstctl) & BIT(24)) >> 24)
+#define PLLnRSTCTL_LOCK(rstctl) (((rstctl) & BIT(23)) >> 23)
+
+#define PLLnCR0(pll) (0x400 + (pll) * 0x100 + 0x4)
+#define PLLnCR0_REFCLK_SEL(cr0) (((cr0) & GENMASK(20, 16)))
+#define PLLnCR0_REFCLK_SEL_100MHZ 0x0
+#define PLLnCR0_REFCLK_SEL_125MHZ 0x10000
+#define PLLnCR0_REFCLK_SEL_156MHZ 0x20000
+#define PLLnCR0_REFCLK_SEL_150MHZ 0x30000
+#define PLLnCR0_REFCLK_SEL_161MHZ 0x40000
+
+#define PLLnCR1(pll) (0x400 + (pll) * 0x100 + 0x8)
+#define PLLnCR1_FRATE_SEL(cr1) (((cr1) & GENMASK(28, 24)))
+#define PLLnCR1_FRATE_5G_10GVCO 0x0
+#define PLLnCR1_FRATE_5G_25GVCO 0x10000000
+#define PLLnCR1_FRATE_10G_20GVCO 0x6000000
/* Per SerDes lane registers */
/* Lane a General Control Register */
-#define LYNX_28G_LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
-#define LYNX_28G_LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
-#define LYNX_28G_LNaGCR0_PROTO_SEL_SGMII 0x8
-#define LYNX_28G_LNaGCR0_PROTO_SEL_XFI 0x50
-#define LYNX_28G_LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
-#define LYNX_28G_LNaGCR0_IF_WIDTH_10_BIT 0x0
-#define LYNX_28G_LNaGCR0_IF_WIDTH_20_BIT 0x2
+#define LNaGCR0(lane) (0x800 + (lane) * 0x100 + 0x0)
+#define LNaGCR0_PROTO_SEL_MSK GENMASK(7, 3)
+#define LNaGCR0_PROTO_SEL_SGMII 0x8
+#define LNaGCR0_PROTO_SEL_XFI 0x50
+#define LNaGCR0_IF_WIDTH_MSK GENMASK(2, 0)
+#define LNaGCR0_IF_WIDTH_10_BIT 0x0
+#define LNaGCR0_IF_WIDTH_20_BIT 0x2
/* Lane a Tx Reset Control Register */
-#define LYNX_28G_LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
-#define LYNX_28G_LNaTRSTCTL_HLT_REQ BIT(27)
-#define LYNX_28G_LNaTRSTCTL_RST_DONE BIT(30)
-#define LYNX_28G_LNaTRSTCTL_RST_REQ BIT(31)
+#define LNaTRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x20)
+#define LNaTRSTCTL_HLT_REQ BIT(27)
+#define LNaTRSTCTL_RST_DONE BIT(30)
+#define LNaTRSTCTL_RST_REQ BIT(31)
/* Lane a Tx General Control Register */
-#define LYNX_28G_LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
-#define LYNX_28G_LNaTGCR0_USE_PLLF 0x0
-#define LYNX_28G_LNaTGCR0_USE_PLLS BIT(28)
-#define LYNX_28G_LNaTGCR0_USE_PLL_MSK BIT(28)
-#define LYNX_28G_LNaTGCR0_N_RATE_FULL 0x0
-#define LYNX_28G_LNaTGCR0_N_RATE_HALF 0x1000000
-#define LYNX_28G_LNaTGCR0_N_RATE_QUARTER 0x2000000
-#define LYNX_28G_LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaTGCR0(lane) (0x800 + (lane) * 0x100 + 0x24)
+#define LNaTGCR0_USE_PLLF 0x0
+#define LNaTGCR0_USE_PLLS BIT(28)
+#define LNaTGCR0_USE_PLL_MSK BIT(28)
+#define LNaTGCR0_N_RATE_FULL 0x0
+#define LNaTGCR0_N_RATE_HALF 0x1000000
+#define LNaTGCR0_N_RATE_QUARTER 0x2000000
+#define LNaTGCR0_N_RATE_MSK GENMASK(26, 24)
-#define LYNX_28G_LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
+#define LNaTECR0(lane) (0x800 + (lane) * 0x100 + 0x30)
/* Lane a Rx Reset Control Register */
-#define LYNX_28G_LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
-#define LYNX_28G_LNaRRSTCTL_HLT_REQ BIT(27)
-#define LYNX_28G_LNaRRSTCTL_RST_DONE BIT(30)
-#define LYNX_28G_LNaRRSTCTL_RST_REQ BIT(31)
-#define LYNX_28G_LNaRRSTCTL_CDR_LOCK BIT(12)
+#define LNaRRSTCTL(lane) (0x800 + (lane) * 0x100 + 0x40)
+#define LNaRRSTCTL_HLT_REQ BIT(27)
+#define LNaRRSTCTL_RST_DONE BIT(30)
+#define LNaRRSTCTL_RST_REQ BIT(31)
+#define LNaRRSTCTL_CDR_LOCK BIT(12)
/* Lane a Rx General Control Register */
-#define LYNX_28G_LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
-#define LYNX_28G_LNaRGCR0_USE_PLLF 0x0
-#define LYNX_28G_LNaRGCR0_USE_PLLS BIT(28)
-#define LYNX_28G_LNaRGCR0_USE_PLL_MSK BIT(28)
-#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
-#define LYNX_28G_LNaRGCR0_N_RATE_FULL 0x0
-#define LYNX_28G_LNaRGCR0_N_RATE_HALF 0x1000000
-#define LYNX_28G_LNaRGCR0_N_RATE_QUARTER 0x2000000
-#define LYNX_28G_LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
-
-#define LYNX_28G_LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
-
-#define LYNX_28G_LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
-#define LYNX_28G_LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
-#define LYNX_28G_LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
-
-#define LYNX_28G_LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
-
-#define LYNX_28G_LNaPSS(lane) (0x1000 + (lane) * 0x4)
-#define LYNX_28G_LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
-#define LYNX_28G_LNaPSS_TYPE_SGMII 0x4
-#define LYNX_28G_LNaPSS_TYPE_XFI 0x28
-
-#define LYNX_28G_SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
-#define LYNX_28G_SGMIIaCR1_SGPCS_EN BIT(11)
-#define LYNX_28G_SGMIIaCR1_SGPCS_DIS 0x0
-#define LYNX_28G_SGMIIaCR1_SGPCS_MSK BIT(11)
+#define LNaRGCR0(lane) (0x800 + (lane) * 0x100 + 0x44)
+#define LNaRGCR0_USE_PLLF 0x0
+#define LNaRGCR0_USE_PLLS BIT(28)
+#define LNaRGCR0_USE_PLL_MSK BIT(28)
+#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+#define LNaRGCR0_N_RATE_FULL 0x0
+#define LNaRGCR0_N_RATE_HALF 0x1000000
+#define LNaRGCR0_N_RATE_QUARTER 0x2000000
+#define LNaRGCR0_N_RATE_MSK GENMASK(26, 24)
+
+#define LNaRGCR1(lane) (0x800 + (lane) * 0x100 + 0x48)
+
+#define LNaRECR0(lane) (0x800 + (lane) * 0x100 + 0x50)
+#define LNaRECR1(lane) (0x800 + (lane) * 0x100 + 0x54)
+#define LNaRECR2(lane) (0x800 + (lane) * 0x100 + 0x58)
+
+#define LNaRSCCR0(lane) (0x800 + (lane) * 0x100 + 0x74)
+
+#define LNaPSS(lane) (0x1000 + (lane) * 0x4)
+#define LNaPSS_TYPE(pss) (((pss) & GENMASK(30, 24)) >> 24)
+#define LNaPSS_TYPE_SGMII 0x4
+#define LNaPSS_TYPE_XFI 0x28
+
+#define SGMIIaCR1(lane) (0x1804 + (lane) * 0x10)
+#define SGMIIaCR1_SGPCS_EN BIT(11)
+#define SGMIIaCR1_SGPCS_DIS 0x0
+#define SGMIIaCR1_SGPCS_MSK BIT(11)
struct lynx_28g_priv;
}
#define lynx_28g_lane_rmw(lane, reg, val, mask) \
- lynx_28g_rmw((lane)->priv, LYNX_28G_##reg(lane->id), \
- LYNX_28G_##reg##_##val, LYNX_28G_##reg##_##mask)
+ lynx_28g_rmw((lane)->priv, reg(lane->id), \
+ reg##_##val, reg##_##mask)
#define lynx_28g_lane_read(lane, reg) \
- ioread32((lane)->priv->base + LYNX_28G_##reg((lane)->id))
+ ioread32((lane)->priv->base + reg((lane)->id))
#define lynx_28g_pll_read(pll, reg) \
- ioread32((pll)->priv->base + LYNX_28G_##reg((pll)->id))
+ ioread32((pll)->priv->base + reg((pll)->id))
static bool lynx_28g_supports_interface(struct lynx_28g_priv *priv, int intf)
{
int i;
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
- if (LYNX_28G_PLLnRSTCTL_DIS(priv->pll[i].rstctl))
+ if (PLLnRSTCTL_DIS(priv->pll[i].rstctl))
continue;
if (test_bit(intf, priv->pll[i].supported))
for (i = 0; i < LYNX_28G_NUM_PLL; i++) {
pll = &priv->pll[i];
- if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
if (test_bit(intf, pll->supported))
struct lynx_28g_pll *pll,
phy_interface_t intf)
{
- switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
- case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case PLLnCR1_FRATE_5G_10GVCO:
+ case PLLnCR1_FRATE_5G_25GVCO:
switch (intf) {
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
break;
}
break;
- case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ case PLLnCR1_FRATE_10G_20GVCO:
switch (intf) {
case PHY_INTERFACE_MODE_10GBASER:
case PHY_INTERFACE_MODE_USXGMII:
static void lynx_28g_cleanup_lane(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
/* Cleanup the protocol configuration registers of the current protocol */
switch (lane->interface) {
case PHY_INTERFACE_MODE_10GBASER:
- lynx_28g_rmw(priv, LYNX_28G_PCCC,
- LYNX_28G_PCCC_SXGMII_DIS << lane_offset,
+ lynx_28g_rmw(priv, PCCC,
+ PCCC_SXGMII_DIS << lane_offset,
GENMASK(3, 0) << lane_offset);
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
- lynx_28g_rmw(priv, LYNX_28G_PCC8,
- LYNX_28G_PCC8_SGMII_DIS << lane_offset,
+ lynx_28g_rmw(priv, PCC8,
+ PCC8_SGMII_DIS << lane_offset,
GENMASK(3, 0) << lane_offset);
break;
default:
static void lynx_28g_lane_set_sgmii(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Setup the lane to run in SGMII */
- lynx_28g_rmw(priv, LYNX_28G_PCC8,
- LYNX_28G_PCC8_SGMII << lane_offset,
+ lynx_28g_rmw(priv, PCC8,
+ PCC8_SGMII << lane_offset,
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_EN, SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x00808006, priv->base + LYNX_28G_LNaTECR0(lane->id));
- iowrite32(0x04310000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
- iowrite32(0x9f800000, priv->base + LYNX_28G_LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR2(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+ iowrite32(0x00808006, priv->base + LNaTECR0(lane->id));
+ iowrite32(0x04310000, priv->base + LNaRGCR1(lane->id));
+ iowrite32(0x9f800000, priv->base + LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRECR2(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRSCCR0(lane->id));
}
static void lynx_28g_lane_set_10gbaser(struct lynx_28g_lane *lane)
{
- u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane);
struct lynx_28g_priv *priv = lane->priv;
+ u32 lane_offset = LNa_PCC_OFFSET(lane);
struct lynx_28g_pll *pll;
lynx_28g_cleanup_lane(lane);
/* Enable the SXGMII lane */
- lynx_28g_rmw(priv, LYNX_28G_PCCC,
- LYNX_28G_PCCC_10GBASER << lane_offset,
+ lynx_28g_rmw(priv, PCCC,
+ PCCC_10GBASER << lane_offset,
GENMASK(3, 0) << lane_offset);
/* Setup the protocol select and SerDes parallel interface width */
lynx_28g_lane_rmw(lane, SGMIIaCR1, SGPCS_DIS, SGPCS_MSK);
/* Configure the appropriate equalization parameters for the protocol */
- iowrite32(0x10808307, priv->base + LYNX_28G_LNaTECR0(lane->id));
- iowrite32(0x10000000, priv->base + LYNX_28G_LNaRGCR1(lane->id));
- iowrite32(0x00000000, priv->base + LYNX_28G_LNaRECR0(lane->id));
- iowrite32(0x001f0000, priv->base + LYNX_28G_LNaRECR1(lane->id));
- iowrite32(0x81000020, priv->base + LYNX_28G_LNaRECR2(lane->id));
- iowrite32(0x00002000, priv->base + LYNX_28G_LNaRSCCR0(lane->id));
+ iowrite32(0x10808307, priv->base + LNaTECR0(lane->id));
+ iowrite32(0x10000000, priv->base + LNaRGCR1(lane->id));
+ iowrite32(0x00000000, priv->base + LNaRECR0(lane->id));
+ iowrite32(0x001f0000, priv->base + LNaRECR1(lane->id));
+ iowrite32(0x81000020, priv->base + LNaRECR2(lane->id));
+ iowrite32(0x00002000, priv->base + LNaRSCCR0(lane->id));
}
static int lynx_28g_power_off(struct phy *phy)
do {
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while ((trstctl & LYNX_28G_LNaTRSTCTL_HLT_REQ) ||
- (rrstctl & LYNX_28G_LNaRRSTCTL_HLT_REQ));
+ } while ((trstctl & LNaTRSTCTL_HLT_REQ) ||
+ (rrstctl & LNaRRSTCTL_HLT_REQ));
lane->powered_up = false;
do {
trstctl = lynx_28g_lane_read(lane, LNaTRSTCTL);
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(trstctl & LYNX_28G_LNaTRSTCTL_RST_DONE) ||
- !(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+ } while (!(trstctl & LNaTRSTCTL_RST_DONE) ||
+ !(rrstctl & LNaRRSTCTL_RST_DONE));
lane->powered_up = true;
pll->cr0 = lynx_28g_pll_read(pll, PLLnCR0);
pll->cr1 = lynx_28g_pll_read(pll, PLLnCR1);
- if (LYNX_28G_PLLnRSTCTL_DIS(pll->rstctl))
+ if (PLLnRSTCTL_DIS(pll->rstctl))
continue;
- switch (LYNX_28G_PLLnCR1_FRATE_SEL(pll->cr1)) {
- case LYNX_28G_PLLnCR1_FRATE_5G_10GVCO:
- case LYNX_28G_PLLnCR1_FRATE_5G_25GVCO:
+ switch (PLLnCR1_FRATE_SEL(pll->cr1)) {
+ case PLLnCR1_FRATE_5G_10GVCO:
+ case PLLnCR1_FRATE_5G_25GVCO:
/* 5GHz clock net */
__set_bit(PHY_INTERFACE_MODE_1000BASEX, pll->supported);
__set_bit(PHY_INTERFACE_MODE_SGMII, pll->supported);
break;
- case LYNX_28G_PLLnCR1_FRATE_10G_20GVCO:
+ case PLLnCR1_FRATE_10G_20GVCO:
/* 10.3125GHz clock net */
__set_bit(PHY_INTERFACE_MODE_10GBASER, pll->supported);
break;
}
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- if (!(rrstctl & LYNX_28G_LNaRRSTCTL_CDR_LOCK)) {
+ if (!(rrstctl & LNaRRSTCTL_CDR_LOCK)) {
lynx_28g_lane_rmw(lane, LNaRRSTCTL, RST_REQ, RST_REQ);
do {
rrstctl = lynx_28g_lane_read(lane, LNaRRSTCTL);
- } while (!(rrstctl & LYNX_28G_LNaRRSTCTL_RST_DONE));
+ } while (!(rrstctl & LNaRRSTCTL_RST_DONE));
}
mutex_unlock(&lane->phy->mutex);
u32 pss, protocol;
pss = lynx_28g_lane_read(lane, LNaPSS);
- protocol = LYNX_28G_LNaPSS_TYPE(pss);
+ protocol = LNaPSS_TYPE(pss);
switch (protocol) {
- case LYNX_28G_LNaPSS_TYPE_SGMII:
+ case LNaPSS_TYPE_SGMII:
lane->interface = PHY_INTERFACE_MODE_SGMII;
break;
- case LYNX_28G_LNaPSS_TYPE_XFI:
+ case LNaPSS_TYPE_XFI:
lane->interface = PHY_INTERFACE_MODE_10GBASER;
break;
default:
projects / thirdparty / linux.git / commitdiff
