arm64: dts: freescale: imx95-verdin: Split UART_2 pinctrl group

Some carrier board reuse the UART_2 control signals as GPIO, split
the pinctrl RTS/CTS in separated nodes to maximize flexibility.

Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>

diff --git a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi
index d3737956e2f9b362700d13fa113e9f63fc188434..72e7f1e884098421b1827ed95111d82fd30743fe 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx95-verdin.dtsi
@@ -541,7 +541,7 @@
 /* Verdin UART_2 */
 &lpuart8 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart8>;
+       pinctrl-0 = <&pinctrl_uart8>, <&pinctrl_uart8_cts>, <&pinctrl_uart8_rts>;
        uart-has-rtscts;
 };
 
@@ -1058,12 +1058,20 @@
                           <IMX95_PAD_GPIO_IO11__LPUART7_RTS_B  0x31e>; /* SODIMM 133 */
        };
 
-       /* Verdin UART_2 */
+       /* Verdin UART_2 CTS */
+       pinctrl_uart8_cts: uart8ctsgrp {
+               fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B  0x31e>; /* SODIMM 143 */
+       };
+
+       /* Verdin UART_2 RTS */
+       pinctrl_uart8_rts: uart8rtsgrp {
+               fsl,pins = <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B  0x31e>; /* SODIMM 141 */
+       };
+
+       /* Verdin UART_2 RX/TX */
        pinctrl_uart8: uart8grp {
                fsl,pins = <IMX95_PAD_GPIO_IO12__LPUART8_TX     0x31e>, /* SODIMM 139 */
-                          <IMX95_PAD_GPIO_IO13__LPUART8_RX     0x31e>, /* SODIMM 137 */
-                          <IMX95_PAD_GPIO_IO14__LPUART8_CTS_B  0x31e>, /* SODIMM 143 */
-                          <IMX95_PAD_GPIO_IO15__LPUART8_RTS_B  0x31e>; /* SODIMM 141 */
+                          <IMX95_PAD_GPIO_IO13__LPUART8_RX     0x31e>; /* SODIMM 137 */
        };
 
        /* On-module eMMC */