aarch64: Fix up aarch64_compare_and_swaphi pattern [PR94368]

2020-04-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	Backport from mainline
	2020-03-31  Jakub Jelinek  <jakub@redhat.com>

	PR target/94368
	* config/aarch64/constraints.md (Uph): New constraint.
	* config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
	(@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
	constraint.

	* gcc.dg/pr94368.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d0fc36b8ddf629ce6aae7beceba9d37c9ac07a8b..25138099ca172180b971075edd21b6a62de6c517 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2020-04-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       Backport from mainline
+       2020-03-31  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/94368
+       * config/aarch64/constraints.md (Uph): New constraint.
+       * config/aarch64/atomics.md (cas_short_expected_imm): New mode attr.
+       (@aarch64_compare_and_swap<mode>): Use it instead of n in operand 2's
+       constraint.
+
 2020-04-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        Backport from mainline

diff --git a/gcc/config/aarch64/atomics.md b/gcc/config/aarch64/atomics.md
index 1458bc000959eed6e39fa82e91853fb40fb0ac8d..590f82a4b14a9b2345d1d36c00da05ecdba415a9 100644 (file)
--- a/gcc/config/aarch64/atomics.md
+++ b/gcc/config/aarch64/atomics.md
@@ -38,6 +38,8 @@
 
 (define_mode_attr cas_short_expected_pred
   [(QI "aarch64_reg_or_imm") (HI "aarch64_plushi_operand")])
+(define_mode_attr cas_short_expected_imm
+  [(QI "n") (HI "Uph")])
 
 (define_insn_and_split "@aarch64_compare_and_swap<mode>"
   [(set (reg:CC CC_REGNUM)                                     ;; bool out
@@ -47,7 +49,8 @@
       (match_operand:SHORT 1 "aarch64_sync_memory_operand" "+Q"))) ;; memory
    (set (match_dup 1)
     (unspec_volatile:SHORT
-      [(match_operand:SHORT 2 "<cas_short_expected_pred>" "rn")        ;; expected
+      [(match_operand:SHORT 2 "<cas_short_expected_pred>"
+                             "r<cas_short_expected_imm>")      ;; expected
        (match_operand:SHORT 3 "aarch64_reg_or_zero" "rZ")      ;; desired
        (match_operand:SI 4 "const_int_operand")                        ;; is_weak
        (match_operand:SI 5 "const_int_operand")                        ;; mod_s

diff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md
index 21f9549e660868900256157ea2f7154164ddd607..73892b339c42e3828592cfb786feda05b1e56db0 100644 (file)
--- a/gcc/config/aarch64/constraints.md
+++ b/gcc/config/aarch64/constraints.md
@@ -220,6 +220,13 @@
   (and (match_code "const_int")
        (match_test "(unsigned) exact_log2 (ival) <= 4")))
 
+(define_constraint "Uph"
+  "@internal
+  A constraint that matches HImode integers zero extendable to
+  SImode plus_operand."
+  (and (match_code "const_int")
+       (match_test "aarch64_plushi_immediate (op, VOIDmode)")))
+
 (define_memory_constraint "Q"
  "A memory address which uses a single base register with no offset."
  (and (match_code "mem")

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e28e47cfa1c1aa30e8885a7a2b4cd27f2f7f8b0b..fbf07ceb56ac2cb006d0f5f21c38658e25047ab8 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,10 @@
+2020-04-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
+
+       Backport from mainline
+       2020-03-31  Jakub Jelinek  <jakub@redhat.com>
+
+       * gcc.dg/pr94368.c: New test.
+
 2020-04-01  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
        Backport from mainline

diff --git a/gcc/testsuite/gcc.dg/pr94368.c b/gcc/testsuite/gcc.dg/pr94368.c
new file mode 100644 (file)
index 0000000..1267b82
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr94368.c
@@ -0,0 +1,25 @@
+/* PR target/94368 */
+/* { dg-do compile { target fpic } } */
+/* { dg-options "-fpic -O1 -fcommon" } */
+
+int b, c, d, e, f, h;
+short g;
+int foo (int) __attribute__ ((__const__));
+
+void
+bar (void)
+{
+  while (1)
+    {
+      while (1)
+       {
+         __atomic_load_n (&e, 0);
+         if (foo (2))
+           __sync_val_compare_and_swap (&c, 0, f);
+         b = 1;
+         if (h == e)
+           break;
+       }
+      __sync_val_compare_and_swap (&g, -1, f);
+    }
+}