Merge r6447 (Test lvxl and stvxl.)

git-svn-id: svn://svn.valgrind.org/valgrind/branches/VALGRIND_3_2_BRANCH@6448

diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
index a051715946b8df4c35901fb4ea1eb4022c19b318..281ae114bfad7ac595767379b6d69555f8803240 100644 (file)
--- a/none/tests/ppc32/jm-insns.c
+++ b/none/tests/ppc32/jm-insns.c
@@ -3051,11 +3051,17 @@ static void test_lvx (void)
     __asm__ __volatile__ ("lvx          17,14,15");
 }
 
+static void test_lvxl (void)
+{
+    __asm__ __volatile__ ("lvxl         17,14,15");
+}
+
 static test_t tests_ald_ops_two[] = {
     { &test_lvebx           , "       lvebx", },
     { &test_lvehx           , "       lvehx", },
     { &test_lvewx           , "       lvewx", },
     { &test_lvx             , "         lvx", },
+    { &test_lvxl            , "        lvxl", },
     { NULL,                   NULL,           },
 };
 #endif /* defined (HAS_ALTIVEC) */
@@ -3081,11 +3087,17 @@ static void test_stvx (void)
     __asm__ __volatile__ ("stvx         14,15,16");
 }
 
+static void test_stvxl (void)
+{
+    __asm__ __volatile__ ("stvxl        14,15,16");
+}
+
 static test_t tests_ast_ops_three[] = {
     { &test_stvebx          , "      stvebx", },
     { &test_stvehx          , "      stvehx", },
     { &test_stvewx          , "      stvewx", },
     { &test_stvx            , "        stvx", },
+    { &test_stvxl           , "       stvxl", },
     { NULL,                   NULL,           },
 };
 #endif /* defined (HAS_ALTIVEC) */

diff --git a/none/tests/ppc32/jm-vmx.stdout.exp b/none/tests/ppc32/jm-vmx.stdout.exp
index ef056615e2ddd44bb6f961b518bf2cdca3c18d32..0a0bb3eb45b3eb3f28fb646ecba73f8c57fd3fc8 100644 (file)
--- a/none/tests/ppc32/jm-vmx.stdout.exp
+++ b/none/tests/ppc32/jm-vmx.stdout.exp
@@ -1474,6 +1474,13 @@ Altivec load insns with two register args:
          lvx   7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
          lvx  14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
 
+        lvxl   0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+        lvxl   7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+        lvxl  14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+        lvxl   0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+        lvxl   7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+        lvxl  14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
 Altivec store insns with three register args:
       stvebx   0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
       stvebx   7, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000008 00000000 00000000 (00000000)
@@ -1503,6 +1510,13 @@ Altivec store insns with three register args:
         stvx   7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
         stvx  14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
 
+       stvxl   0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+       stvxl   7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+       stvxl  14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
+       stvxl   0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+       stvxl   7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+       stvxl  14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
+
 Altivec floating point arith insns with three args:
 Altivec floating point arith insns with two args:
       vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
@@ -3019,4 +3033,4 @@ Altivec float special insns:
       vctsxs: ffbfffff (          nan), 18 => 00000000 ( 0.000000e+00) (00000000)
       vctsxs: ffbfffff (          nan), 27 => 00000000 ( 0.000000e+00) (00000000)
 
-All done. Tested 161 different instructions
+All done. Tested 163 different instructions