arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH

Enable MT25QU512ABB8E12 FLASH connected to XSPI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250704140823.163572-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
index 6c0aee6960f443c36eb53b212b32d1d2782bf583..5c3f4e471e3de99455b82f871455263ecfbe2fb0 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
+++ b/arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts
@@ -370,6 +370,18 @@
                        pinmux = <RZV2H_PORT_PINMUX(6, 6, 14)>; /* VBUS */
                };
        };
+
+       xspi_pins: xspi0 {
+               ctrl {
+                       pins = "XSPI0_RESET0N", "XSPI0_CS0N", "XSPI0_CKP";
+                       output-enable;
+               };
+
+               io {
+                       pins = "XSPI0_IO0", "XSPI0_IO1", "XSPI0_IO2", "XSPI0_IO3";
+                       renesas,output-impedance = <3>;
+               };
+       };
 };
 
 &qextal_clk {
@@ -424,3 +436,46 @@
 &wdt1 {
        status = "okay";
 };
+
+&xspi {
+       pinctrl-0 = <&xspi_pins>;
+       pinctrl-names = "default";
+       /*
+        * MT25QU512ABB8E12 flash chip is capable of running at 166MHz
+        * clock frequency. Set the clock frequency to the maximum 133MHz
+        * supported by the RZ/V2H SoC.
+        */
+       assigned-clocks = <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>;
+       assigned-clock-rates = <133333334>;
+       status = "okay";
+
+       flash@0 {
+               compatible = "jedec,spi-nor";
+               reg = <0>;
+               vcc-supply = <&reg_1p8v>;
+               m25p,fast-read;
+               spi-tx-bus-width = <4>;
+               spi-rx-bus-width = <4>;
+
+               partitions {
+                       compatible = "fixed-partitions";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+
+                       partition@0 {
+                               label = "bl2";
+                               reg = <0x00000000 0x00060000>;
+                       };
+
+                       partition@60000 {
+                               label = "fip";
+                               reg = <0x00060000 0x1fa0000>;
+                       };
+
+                       partition@2000000 {
+                               label = "user";
+                               reg = <0x2000000 0x2000000>;
+                       };
+               };
+       };
+};