]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
arm64: dts: renesas: r9a09g047: Add WDT1-WDT3 nodes
authorBiju Das <biju.das.jz@bp.renesas.com>
Wed, 15 Jan 2025 10:38:53 +0000 (10:38 +0000)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 21 Feb 2025 15:23:00 +0000 (16:23 +0100)
Add WDT1-WDT3 nodes to RZ/G3E ("R9A09G047") SoC DTSI.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250115103858.104709-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
arch/arm64/boot/dts/renesas/r9a09g047.dtsi

index 200e9ea8919354baf2179324f351b644aab77c70..133aa3272d3a73817b733e665cf06c36f0cada32 100644 (file)
                        status = "disabled";
                };
 
+               wdt1: watchdog@14400000 {
+                       compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+                       reg = <0 0x14400000 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x76>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt2: watchdog@13000000 {
+                       compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+                       reg = <0 0x13000000 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x77>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
+               wdt3: watchdog@13000400 {
+                       compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt";
+                       reg = <0 0x13000400 0 0x400>;
+                       clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>;
+                       clock-names = "pclk", "oscclk";
+                       resets = <&cpg 0x78>;
+                       power-domains = <&cpg>;
+                       status = "disabled";
+               };
+
                i2c0: i2c@14400400 {
                        compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057";
                        reg = <0 0x14400400 0 0x400>;