bpf: ISA V4 sign-extending move and load insns [PR110782,PR110784]

BPF ISA V4 introduces sign-extending move and load operations.  This
patch makes the BPF backend generate those instructions, when enabled
and useful.

A new option, -m[no-]smov gates generation of these instructions, and is
enabled by default for -mcpu=v4 and above.  Tests for the new
instructions and documentation for the new options are included.

	PR target/110782
	PR target/110784

gcc/

	* config/bpf/bpf.opt (msmov): New option.
	* config/bpf/bpf.cc (bpf_option_override): Handle it here.
	* config/bpf/bpf.md (*extendsidi2): New.
	(extendhidi2): New.
	(extendqidi2): New.
	(extendsisi2): New.
	(extendhisi2): New.
	(extendqisi2): New.
	* doc/invoke.texi (Option Summary): Add -msmov eBPF option.
	(eBPF Options): Add -m[no-]smov.  Document that -mcpu=v4
	also enables -msmov.

gcc/testsuite/

	* gcc.target/bpf/sload-1.c: New test.
	* gcc.target/bpf/sload-pseudoc-1.c: New test.
	* gcc.target/bpf/smov-1.c: New test.
	* gcc.target/bpf/smov-pseudoc-1.c: New test.

diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc
index 0e07b416add8b319adc480a616f327d41a4ac534..b5b5674edbb5d9e571604eecfb7b99b0a8ddd3ae 100644 (file)
--- a/gcc/config/bpf/bpf.cc
+++ b/gcc/config/bpf/bpf.cc
@@ -262,6 +262,9 @@ bpf_option_override (void)
   if (bpf_has_sdiv == -1)
     bpf_has_sdiv = (bpf_isa >= ISA_V4);
 
+  if (bpf_has_smov == -1)
+    bpf_has_smov = (bpf_isa >= ISA_V4);
+
   /* Disable -fstack-protector as it is not supported in BPF.  */
   if (flag_stack_protect)
     {

diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index 66436397bb78fd508439ca5a00b20748e46d30dd..a69a239b9d6a0124bd03ac535010df16d841a0f1 100644 (file)
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -307,6 +307,56 @@
   DONE;
 })
 
+;; ISA V4 introduces sign-extending move and load operations.
+
+(define_insn "*extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,32|%0 = (s32) %1}
+   {ldxsw\t%0,%1|%0 = *(s32 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,16|%0 = (s16) %1}
+   {ldxsh\t%0,%1|%0 = *(s16 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,8|%0 = (s8) %1}
+   {ldxsb\t%0,%1|%0 = *(s8 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendsisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,32|%w0 = (s32) %w1}"
+  [(set_attr "type" "alu")])
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,16|%w0 = (s16) %w1}"
+  [(set_attr "type" "alu")])
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,8|%w0 = (s8) %w1}"
+  [(set_attr "type" "alu")])
+
 ;;;; Data movement
 
 (define_mode_iterator MM [QI HI SI DI SF DF])

diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt
index b21cfcab9ea79346ae86622fab7b68d2fb9a1d6a..8e240d397e4ca2824d49e968e47d01e0340b23a9 100644 (file)
--- a/gcc/config/bpf/bpf.opt
+++ b/gcc/config/bpf/bpf.opt
@@ -71,6 +71,10 @@ msdiv
 Target Var(bpf_has_sdiv) Init(-1)
 Enable signed division and modulus instructions.
 
+msmov
+Target Var(bpf_has_smov) Init(-1)
+Enable signed move and memory load instructions.
+
 mcpu=
 Target RejectNegative Joined Var(bpf_isa) Enum(bpf_isa) Init(ISA_V4)
 

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 91113dd5821dc6b2f05f6749901379d607ede7f1..578b4c31e4ccbf62309e06d7944e9c37e34816b9 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -947,7 +947,7 @@ Objective-C and Objective-C++ Dialects}.
 @emph{eBPF Options}
 @gccoptlist{-mbig-endian -mlittle-endian
 -mframe-limit=@var{bytes} -mxbpf -mco-re -mno-co-re -mjmpext
--mjmp32 -malu32 -mv3-atomics -mbswap -msdiv -mcpu=@var{version}
+-mjmp32 -malu32 -mv3-atomics -mbswap -msdiv -msmov -mcpu=@var{version}
 -masm=@var{dialect}}
 
 @emph{FR30 Options}
@@ -24718,6 +24718,12 @@ Enable or disable byte swap instructions.  Enabled for CPU v4 and above.
 Enable or disable signed division and modulus instructions.  Enabled for
 CPU v4 and above.
 
+@opindex msmov
+@item -msmov
+@itemx -mno-smov
+Enable or disable sign-extending move and memory load instructions.
+Enabled for CPU v4 and above.
+
 @opindex mcpu
 @item -mcpu=@var{version}
 This specifies which version of the eBPF ISA to target. Newer versions
@@ -24745,6 +24751,7 @@ All features of v3, plus:
 @itemize @minus
 @item Byte swap instructions, as in @option{-mbswap}
 @item Signed division and modulus instructions, as in @option{-msdiv}
+@item Sign-extending move and memory load instructions, as in @option{-msmov}
 @end itemize
 @end table
 

diff --git a/gcc/testsuite/gcc.target/bpf/sload-1.c b/gcc/testsuite/gcc.target/bpf/sload-1.c
new file mode 100644 (file)
index 0000000..d858229
--- /dev/null
+++ b/gcc/testsuite/gcc.target/bpf/sload-1.c
@@ -0,0 +1,16 @@
+/* Check ISA V4 signed load instructions.  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=v4 -O2" } */
+
+long foo (char *p1, short *p2, int *p3)
+{
+  long x = *p1;
+  long y = *p2;
+  long z = *p3;
+
+  return x + y + z;
+}
+
+/* { dg-final { scan-assembler {ldxsb\t%r.,\[%r.\+-?[0-9]+\]\n} } }  */
+/* { dg-final { scan-assembler {ldxsh\t%r.,\[%r.\+-?[0-9]+\]\n} } }  */
+/* { dg-final { scan-assembler {ldxsw\t%r.,\[%r.\+-?[0-9]+\]\n} } }  */

diff --git a/gcc/testsuite/gcc.target/bpf/sload-pseudoc-1.c b/gcc/testsuite/gcc.target/bpf/sload-pseudoc-1.c
new file mode 100644 (file)
index 0000000..5ac5548
--- /dev/null
+++ b/gcc/testsuite/gcc.target/bpf/sload-pseudoc-1.c
@@ -0,0 +1,16 @@
+/* Check ISA V4 signed load instructions (pseudo-C dialect).  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=v4 -O2 -masm=pseudoc" } */
+
+long foo (char *p1, short *p2, int *p3)
+{
+  long x = *p1;
+  long y = *p2;
+  long z = *p3;
+
+  return x + y + z;
+}
+
+/* { dg-final { scan-assembler {r. = \*\(s8 \*\) \(r.\+-?[0-9]+\)\n} } } */
+/* { dg-final { scan-assembler {r. = \*\(s16 \*\) \(r.\+-?[0-9]+\)\n} } } */
+/* { dg-final { scan-assembler {r. = \*\(s32 \*\) \(r.\+-?[0-9]+\)\n} } } */

diff --git a/gcc/testsuite/gcc.target/bpf/smov-1.c b/gcc/testsuite/gcc.target/bpf/smov-1.c
new file mode 100644 (file)
index 0000000..ec17ad0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/bpf/smov-1.c
@@ -0,0 +1,18 @@
+/* Check signed mov instructions.  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=v4 -O2" } */
+
+long
+foo (char a, short b, int c, unsigned long d)
+{
+  long x = a;
+  long y = b;
+  long z = c;
+  long w = (long) d;
+
+  return x + y + z + w;
+}
+
+/* { dg-final { scan-assembler {movs\t%r.,%r.,8\n} } } */
+/* { dg-final { scan-assembler {movs\t%r.,%r.,16\n} } } */
+/* { dg-final { scan-assembler {movs\t%r.,%r.,32\n} } } */

diff --git a/gcc/testsuite/gcc.target/bpf/smov-pseudoc-1.c b/gcc/testsuite/gcc.target/bpf/smov-pseudoc-1.c
new file mode 100644 (file)
index 0000000..b15334e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/bpf/smov-pseudoc-1.c
@@ -0,0 +1,18 @@
+/* Check signed mov instructions (pseudo-C asm dialect).  */
+/* { dg-do compile } */
+/* { dg-options "-mcpu=v4 -O2 -masm=pseudoc" } */
+
+long
+foo (char a, short b, int c, unsigned long d)
+{
+  long x = a;
+  long y = b;
+  long z = c;
+  long w = (long) d;
+
+  return x + y + z + w;
+}
+
+/* { dg-final { scan-assembler {r. = \(s8\) r.\n} } } */
+/* { dg-final { scan-assembler {r. = \(s16\) r.\n} } } */
+/* { dg-final { scan-assembler {r. = \(s32\) r.\n} } } */