bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- sdhci0: sdhci@f1040000 {
- compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xf1040000 0x0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200 &clk200>;
- no-1-8-v;
- xlnx,mio-bank = <0>;
- };
+ sdhci0: sdhci@f1040000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xf1040000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200 &clk200>;
+ no-1-8-v;
+ xlnx,mio-bank = <0>;
};
aliases {
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- sdhci1: sdhci@f1050000 {
- compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xf1050000 0x0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200 &clk200>;
- no-1-8-v;
- xlnx,mio-bank = <0>;
- };
+ sdhci1: sdhci@f1050000 {
+ compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xf1050000 0x0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200 &clk200>;
+ no-1-8-v;
+ xlnx,mio-bank = <0>;
};
aliases {
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- ospi: spi@f1010000 {
- compatible = "cdns,qspi-nor";
- status = "okay";
- reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
- clock-names = "ref_clk", "pclk";
- clocks = <&clk125 &clk125>;
- bus-num = <2>;
- num-cs = <1>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,is-dma = <1>;
- cdns,trigger-address = <0xc0000000>;
- #address-cells = <1>;
- #size-cells = <0>;
+ ospi: spi@f1010000 {
+ compatible = "cdns,qspi-nor";
+ status = "okay";
+ reg = <0 0xf1010000 0 0x10000 0 0xc0000000 0 0x20000000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clk125 &clk125>;
+ bus-num = <2>;
+ num-cs = <1>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,is-dma = <1>;
+ cdns,trigger-address = <0xc0000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <20000000>;
- no-wp;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <20000000>;
+ no-wp;
};
};
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- qspi: spi@f1030000 {
- compatible = "xlnx,versal-qspi-1.0";
- status = "okay";
- clock-names = "ref_clk", "pclk";
- num-cs = <0x1>;
- reg = <0x0 0xf1030000 0x0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk150 &clk150>;
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <0x1>;
+ reg = <0x0 0xf1030000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk150 &clk150>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0x0>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0x0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
};
};
/*
* dts file for Xilinx Versal NET Mini eMMC Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci1: mmc@f1050000 {
- compatible = "xlnx,versal-net-emmc";
- status = "okay";
- non-removable;
- disable-wp;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0 0xf1050000 0 0x10000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk200>, <&clk200>;
- xlnx,mio-bank = <0>;
- };
+ sdhci1: mmc@f1050000 {
+ compatible = "xlnx,versal-net-emmc";
+ status = "okay";
+ non-removable;
+ disable-wp;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0 0xf1050000 0 0x10000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk200>, <&clk200>;
+ xlnx,mio-bank = <0>;
};
};
/*
* dts file for Xilinx Versal NET Mini OSPI Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <0x2>;
- #size-cells = <0x2>;
- ranges;
-
- ospi: spi@f1010000 {
- compatible = "cdns,qspi-nor";
- status = "okay";
- reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
- clock-names = "ref_clk", "pclk";
- clocks = <&clk125>, <&clk125>;
- bus-num = <2>;
- num-cs = <1>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,is-dma = <1>;
- cdns,is-stig-pgm = <1>;
- cdns,trigger-address = <0xc0000000>;
- #address-cells = <1>;
- #size-cells = <0>;
+ ospi: spi@f1010000 {
+ compatible = "cdns,qspi-nor";
+ status = "okay";
+ reg = <0 0xf1010000 0 0x10000>, <0 0xc0000000 0 0x20000000>;
+ clock-names = "ref_clk", "pclk";
+ clocks = <&clk125>, <&clk125>;
+ bus-num = <2>;
+ num-cs = <1>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,is-dma = <1>;
+ cdns,is-stig-pgm = <1>;
+ cdns,trigger-address = <0xc0000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
- flash0: flash@0 {
- compatible = "mt35xu02g", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <20000000>;
- no-wp;
- };
+ flash0: flash@0 {
+ compatible = "mt35xu02g", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <8>;
+ spi-rx-bus-width = <8>;
+ spi-max-frequency = <20000000>;
+ no-wp;
};
};
};
/*
* dts file for Xilinx Versal NET Mini QSPI Configuration
*
- * (C) Copyright 2023, Advanced Micro Devices, Inc.
+ * (C) Copyright 2023-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
* Ashok Reddy Soma <ashok.reddy.soma@amd.com>
bootph-all;
};
- amba: axi {
- bootph-all;
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- qspi: spi@f1030000 {
- compatible = "xlnx,versal-qspi-1.0";
- status = "okay";
- clock-names = "ref_clk", "pclk";
- num-cs = <1>;
- reg = <0 0xf1030000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&clk150>, <&clk150>;
+ qspi: spi@f1030000 {
+ compatible = "xlnx,versal-qspi-1.0";
+ status = "okay";
+ clock-names = "ref_clk", "pclk";
+ num-cs = <1>;
+ reg = <0 0xf1030000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clk150>, <&clk150>;
- flash0: flash@0 {
- compatible = "n25q512a", "micron,m25p80",
- "jedec,spi-nor";
- reg = <0>;
- spi-tx-bus-width = <4>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <20000000>;
- };
+ flash0: flash@0 {
+ compatible = "n25q512a", "micron,m25p80",
+ "jedec,spi-nor";
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <20000000>;
};
};
};
* dts file for Xilinx Versal NET
*
* Copyright (C) 2021 - 2022, Xilinx, Inc.
- * Copyright (C) 2022, Advanced Micro Devices, Inc.
+ * Copyright (C) 2022-2025, Advanced Micro Devices, Inc.
*
* Michal Simek <michal.simek@amd.com>
*/
bootph-all;
};
- amba: axi {
- compatible = "simple-bus";
+ serial0: serial@f1920000 {
bootph-all;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- serial0: serial@f1920000 {
- bootph-all;
- compatible = "arm,pl011", "arm,primecell";
- reg = <0 0xf1920000 0 0x1000>;
- reg-io-width = <4>;
- clock-names = "uartclk", "apb_pclk";
- clocks = <&clk1>, <&clk1>;
- clock = <1000000>;
- skip-init;
- };
+ compatible = "arm,pl011", "arm,primecell";
+ reg = <0 0xf1920000 0 0x1000>;
+ reg-io-width = <4>;
+ clock-names = "uartclk", "apb_pclk";
+ clocks = <&clk1>, <&clk1>;
+ clock = <1000000>;
+ skip-init;
};
};
clock-frequency = <200000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci0: mmc@ff160000 {
- bootph-all;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- non-removable;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xff160000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk_xin &clk_xin>;
- };
+ sdhci0: mmc@ff160000 {
+ bootph-all;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xff160000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
};
};
clock-frequency = <200000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- sdhci1: mmc@ff170000 {
- bootph-all;
- compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
- status = "disabled";
- non-removable;
- no-sd;
- no-sdio;
- cap-mmc-hw-reset;
- bus-width = <8>;
- reg = <0x0 0xff170000 0x0 0x1000>;
- clock-names = "clk_xin", "clk_ahb";
- clocks = <&clk_xin &clk_xin>;
- };
+ sdhci1: mmc@ff170000 {
+ bootph-all;
+ compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
+ status = "disabled";
+ non-removable;
+ no-sd;
+ no-sdio;
+ cap-mmc-hw-reset;
+ bus-width = <8>;
+ reg = <0x0 0xff170000 0x0 0x1000>;
+ clock-names = "clk_xin", "clk_ahb";
+ clocks = <&clk_xin &clk_xin>;
};
};
bootph-all;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- nand0: nand@ff100000 {
- compatible = "arasan,nfc-v3p10";
- status = "okay";
- reg = <0x0 0xff100000 0x1000>;
- clock-names = "clk_sys", "clk_flash";
- #address-cells = <1>;
- #size-cells = <0>;
- arasan,has-mdma;
- num-cs = <2>;
- nand@0 {
- reg = <0>;
- #address-cells = <2>;
- #size-cells = <1>;
- nand-ecc-mode = "hw";
- };
+ nand0: nand@ff100000 {
+ compatible = "arasan,nfc-v3p10";
+ status = "okay";
+ reg = <0x0 0xff100000 0x1000>;
+ clock-names = "clk_sys", "clk_flash";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ arasan,has-mdma;
+ num-cs = <2>;
+ nand@0 {
+ reg = <0>;
+ #address-cells = <2>;
+ #size-cells = <1>;
+ nand-ecc-mode = "hw";
};
};
};
clock-frequency = <125000000>;
};
- amba: axi {
- compatible = "simple-bus";
- #address-cells = <2>;
- #size-cells = <1>;
- ranges;
-
- qspi: spi@ff0f0000 {
- compatible = "xlnx,zynqmp-qspi-1.0";
- status = "disabled";
- clock-names = "ref_clk", "pclk";
- clocks = <&misc_clk &misc_clk>;
- num-cs = <1>;
- reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
+ qspi: spi@ff0f0000 {
+ compatible = "xlnx,zynqmp-qspi-1.0";
+ status = "disabled";
+ clock-names = "ref_clk", "pclk";
+ clocks = <&misc_clk &misc_clk>;
+ num-cs = <1>;
+ reg = <0x0 0xff0f0000 0x1000 0x0 0xc0000000 0x8000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
};
};
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
# CONFIG_GZIP is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
CONFIG_ARM_DCC=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
CONFIG_MMC_HS200_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ZYNQ=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_DM_SPI_FLASH=y
# CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG is not set
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set
# CONFIG_INPUT is not set
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
CONFIG_ARM_DCC=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_DM_MAILBOX is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_DM_MAILBOX is not set
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_SDHCI=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
CONFIG_DM_MTD=y
CONFIG_ENV_RELOC_GD_ENV_ADDR=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_DM_MAILBOX is not set
# CONFIG_MMC is not set
CONFIG_DM_MTD=y
CONFIG_NO_NET=y
# CONFIG_DM_DEVICE_REMOVE is not set
CONFIG_SPL_DM_SEQ_ALIAS=y
+# CONFIG_SIMPLE_BUS is not set
# CONFIG_FIRMWARE is not set
# CONFIG_GPIO is not set
# CONFIG_I2C is not set