x86/cpu: Restore AMD's DE_CFG MSR after resume

commit 2632daebafd04746b4b96c2f26a6021bc38f6209 upstream.

DE_CFG contains the LFENCE serializing bit, restore it on resume too.
This is relevant to older families due to the way how they do S3.

Unify and correct naming while at it.

Fixes: e4d0e84e4907 ("x86/cpu/AMD: Make LFENCE a serializing instruction")
Reported-by: Andrew Cooper <Andrew.Cooper3@citrix.com>
Reported-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: <stable@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 144dc164b7596a5c13e22f21b58665116ceb54eb..5a8ee3b83af2a8c375374e55cd0f456560a7d9f3 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -489,6 +489,11 @@
 #define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
+
+#define MSR_AMD64_DE_CFG               0xc0011029
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT   1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+
 #define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
@@ -565,9 +570,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
-#define MSR_F10H_DECFG                 0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 8b9e3277a6ceb1a21d5ab506bf04d34e5ef520c8..ec3fa4dc9031847a0d10b212a91372e9cb268de8 100644 (file)
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -822,8 +822,6 @@ static void init_amd_gh(struct cpuinfo_x86 *c)
                set_cpu_bug(c, X86_BUG_AMD_TLB_MMATCH);
 }
 
-#define MSR_AMD64_DE_CFG       0xC0011029
-
 static void init_amd_ln(struct cpuinfo_x86 *c)
 {
        /*
@@ -1018,8 +1016,8 @@ static void init_amd(struct cpuinfo_x86 *c)
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
                 */
-               msr_set_bit(MSR_F10H_DECFG,
-                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+               msr_set_bit(MSR_AMD64_DE_CFG,
+                           MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
 
                /* A serializing LFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index 774ca6bfda9f4c463d4368f0ba8063cab05c4193..205fa420ee7ca582ad50a7b9ae8184c65c8f1fbe 100644 (file)
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -342,8 +342,8 @@ static void init_hygon(struct cpuinfo_x86 *c)
                 * msr_set_bit() uses the safe accessors, too, even if the MSR
                 * is not present.
                 */
-               msr_set_bit(MSR_F10H_DECFG,
-                           MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT);
+               msr_set_bit(MSR_AMD64_DE_CFG,
+                           MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
 
                /* A serializing LFENCE stops RDTSC speculation */
                set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);

diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c
index a0512a91760d2b8f43b8e72c006fa1af8aead290..2b7528821577c13b3695a8f187e2ac9dc9cffac9 100644 (file)
--- a/arch/x86/kvm/svm/svm.c
+++ b/arch/x86/kvm/svm/svm.c
@@ -2475,9 +2475,9 @@ static int svm_get_msr_feature(struct kvm_msr_entry *msr)
        msr->data = 0;
 
        switch (msr->index) {
-       case MSR_F10H_DECFG:
-               if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
-                       msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
+       case MSR_AMD64_DE_CFG:
+               if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC))
+                       msr->data |= MSR_AMD64_DE_CFG_LFENCE_SERIALIZE;
                break;
        case MSR_IA32_PERF_CAPABILITIES:
                return 0;
@@ -2584,7 +2584,7 @@ static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
                        msr_info->data = 0x1E;
                }
                break;
-       case MSR_F10H_DECFG:
+       case MSR_AMD64_DE_CFG:
                msr_info->data = svm->msr_decfg;
                break;
        default:
@@ -2764,7 +2764,7 @@ static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
        case MSR_VM_IGNNE:
                vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
                break;
-       case MSR_F10H_DECFG: {
+       case MSR_AMD64_DE_CFG: {
                struct kvm_msr_entry msr_entry;
 
                msr_entry.index = msr->index;

diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 0ac80b3ff0f5bf5719d7da9a4a7038a45732f4ce..23d7c563e012b358d661efb3e74415365718703b 100644 (file)
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -1362,7 +1362,7 @@ static const u32 msr_based_features_all[] = {
        MSR_IA32_VMX_EPT_VPID_CAP,
        MSR_IA32_VMX_VMFUNC,
 
-       MSR_F10H_DECFG,
+       MSR_AMD64_DE_CFG,
        MSR_IA32_UCODE_REV,
        MSR_IA32_ARCH_CAPABILITIES,
        MSR_IA32_PERF_CAPABILITIES,

diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c
index d023c85e3c53616c6fc23db19e2620ba925fd5f7..61581c45788e3bb57b796048e71451659b9f7540 100644 (file)
--- a/arch/x86/power/cpu.c
+++ b/arch/x86/power/cpu.c
@@ -522,6 +522,7 @@ static void pm_save_spec_msr(void)
                MSR_TSX_FORCE_ABORT,
                MSR_IA32_MCU_OPT_CTRL,
                MSR_AMD64_LS_CFG,
+               MSR_AMD64_DE_CFG,
        };
 
        msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id));

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 144dc164b7596a5c13e22f21b58665116ceb54eb..8fb9256768134d3f4be5a0946f644c7424c9bbb3 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -489,6 +489,11 @@
 #define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
+
+#define MSR_AMD64_DE_CFG               0xc0011029
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT  1
+#define MSR_AMD64_DE_CFG_LFENCE_SERIALIZE      BIT_ULL(MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT)
+
 #define MSR_AMD64_BU_CFG2              0xc001102a
 #define MSR_AMD64_IBSFETCHCTL          0xc0011030
 #define MSR_AMD64_IBSFETCHLINAD                0xc0011031
@@ -565,9 +570,6 @@
 #define FAM10H_MMIO_CONF_BASE_MASK     0xfffffffULL
 #define FAM10H_MMIO_CONF_BASE_SHIFT    20
 #define MSR_FAM10H_NODE_ID             0xc001100c
-#define MSR_F10H_DECFG                 0xc0011029
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT    1
-#define MSR_F10H_DECFG_LFENCE_SERIALIZE                BIT_ULL(MSR_F10H_DECFG_LFENCE_SERIALIZE_BIT)
 
 /* K8 MSRs */
 #define MSR_K8_TOP_MEM1                        0xc001001a