AVB5_AVTP_MATCH_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - CANFD0 ----------------------------------------------------------------- */
static const unsigned int canfd0_data_pins[] = {
/* CANFD0_TX, CANFD0_RX */
static const unsigned int du_oddf_mux[] = {
DU_ODDF_DISP_CDE_MARK,
};
+#endif
/* - HSCIF0 ----------------------------------------------------------------- */
static const unsigned int hscif0_data_pins[] = {
SDA6_MARK, SCL6_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - INTC-EX ---------------------------------------------------------------- */
static const unsigned int intc_ex_irq0_pins[] = {
/* IRQ0 */
static const unsigned int intc_ex_irq5_mux[] = {
IRQ5_MARK,
};
+#endif
/* - MMC -------------------------------------------------------------------- */
static const unsigned int mmc_data_pins[] = {
MMC_DS_MARK,
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_clk_pins[] = {
/* MSIOF0_SCK */
static const unsigned int pwm4_mux[] = {
PWM4_MARK,
};
+#endif
/* - QSPI0 ------------------------------------------------------------------ */
static const unsigned int qspi0_ctrl_pins[] = {
SH_PFC_PIN_GROUP(avb5_avtp_capture),
SH_PFC_PIN_GROUP(avb5_avtp_match),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(canfd0_data),
SH_PFC_PIN_GROUP(canfd1_data),
SH_PFC_PIN_GROUP(canfd2_data),
SH_PFC_PIN_GROUP(du_clk_out),
SH_PFC_PIN_GROUP(du_sync),
SH_PFC_PIN_GROUP(du_oddf),
+#endif
SH_PFC_PIN_GROUP(hscif0_data),
SH_PFC_PIN_GROUP(hscif0_clk),
SH_PFC_PIN_GROUP(i2c5),
SH_PFC_PIN_GROUP(i2c6),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(intc_ex_irq0),
SH_PFC_PIN_GROUP(intc_ex_irq1),
SH_PFC_PIN_GROUP(intc_ex_irq2),
SH_PFC_PIN_GROUP(intc_ex_irq3),
SH_PFC_PIN_GROUP(intc_ex_irq4),
SH_PFC_PIN_GROUP(intc_ex_irq5),
+#endif
BUS_DATA_PIN_GROUP(mmc_data, 1),
BUS_DATA_PIN_GROUP(mmc_data, 4),
SH_PFC_PIN_GROUP(mmc_wp),
SH_PFC_PIN_GROUP(mmc_ds),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_PIN_GROUP(msiof0_clk),
SH_PFC_PIN_GROUP(msiof0_sync),
SH_PFC_PIN_GROUP(msiof0_ss1),
SH_PFC_PIN_GROUP(pwm2),
SH_PFC_PIN_GROUP(pwm3),
SH_PFC_PIN_GROUP(pwm4),
+#endif
SH_PFC_PIN_GROUP(qspi0_ctrl),
BUS_DATA_PIN_GROUP(qspi0_data, 2),
"avb5_avtp_match",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const canfd0_groups[] = {
"canfd0_data",
};
"du_sync",
"du_oddf",
};
+#endif
static const char * const hscif0_groups[] = {
"hscif0_data",
"i2c6",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const intc_ex_groups[] = {
"intc_ex_irq0",
"intc_ex_irq1",
"intc_ex_irq4",
"intc_ex_irq5",
};
+#endif
static const char * const mmc_groups[] = {
"mmc_data1",
"mmc_ds",
};
+#ifdef CONFIG_PINCTRL_PFC_FULL
static const char * const msiof0_groups[] = {
"msiof0_clk",
"msiof0_sync",
static const char * const pwm4_groups[] = {
"pwm4",
};
+#endif
static const char * const qspi0_groups[] = {
"qspi0_ctrl",
SH_PFC_FUNCTION(avb4),
SH_PFC_FUNCTION(avb5),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(canfd0),
SH_PFC_FUNCTION(canfd1),
SH_PFC_FUNCTION(canfd2),
SH_PFC_FUNCTION(can_clk),
SH_PFC_FUNCTION(du),
+#endif
SH_PFC_FUNCTION(hscif0),
SH_PFC_FUNCTION(hscif1),
SH_PFC_FUNCTION(i2c5),
SH_PFC_FUNCTION(i2c6),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(intc_ex),
+#endif
SH_PFC_FUNCTION(mmc),
+#ifdef CONFIG_PINCTRL_PFC_FULL
SH_PFC_FUNCTION(msiof0),
SH_PFC_FUNCTION(msiof1),
SH_PFC_FUNCTION(msiof2),
SH_PFC_FUNCTION(pwm2),
SH_PFC_FUNCTION(pwm3),
SH_PFC_FUNCTION(pwm4),
+#endif
SH_PFC_FUNCTION(qspi0),
SH_PFC_FUNCTION(qspi1),