]> git.ipfire.org Git - thirdparty/kernel/linux.git/commitdiff
arm64: dts: cavium: thunder-88xx: Add missing PL011 "uartclk"
authorRob Herring (Arm) <robh@kernel.org>
Tue, 16 Dec 2025 18:01:37 +0000 (12:01 -0600)
committerKrzysztof Kozlowski <krzk@kernel.org>
Mon, 22 Dec 2025 10:03:58 +0000 (11:03 +0100)
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20251216180136.2794105-2-robh@kernel.org
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi

index cc860a80af516c903a4a65c8faf01c21c5c0a5cc..70430cb2b053a4628b9708554899d641baba04c2 100644 (file)
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x87e0 0x24000000 0x0 0x1000>;
                        interrupts = <1 21 4>;
-                       clocks = <&refclk50mhz>;
-                       clock-names = "apb_pclk";
+                       clocks = <&refclk50mhz>, <&refclk50mhz>;
+                       clock-names = "uartclk", "apb_pclk";
                };
 
                uaa1: serial@87e025000000 {
                        compatible = "arm,pl011", "arm,primecell";
                        reg = <0x87e0 0x25000000 0x0 0x1000>;
                        interrupts = <1 22 4>;
-                       clocks = <&refclk50mhz>;
-                       clock-names = "apb_pclk";
+                       clocks = <&refclk50mhz>, <&refclk50mhz>;
+                       clock-names = "uartclk", "apb_pclk";
                };
        };
 };