clk: qcom: Add support for GPU Clock Controller on QCS8300

The QCS8300 GPU clock controller is a derivative of SA8775P, but has few
additional clocks and minor differences. Hence, add support for QCS8300
GPU clock controller, by extending the SA8775P GPUCC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Link: https://lore.kernel.org/r/20250109-qcs8300-mm-patches-new-v4-2-63e8ac268b02@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/drivers/clk/qcom/gpucc-sa8775p.c b/drivers/clk/qcom/gpucc-sa8775p.c
index f8a8ac343d70a89ae99ea5485cd9b0dc8f9d7db6..78cad622cb5a08bbde890dc6a33c2a24538901d9 100644 (file)
--- a/drivers/clk/qcom/gpucc-sa8775p.c
+++ b/drivers/clk/qcom/gpucc-sa8775p.c
@@ -12,7 +12,7 @@
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
 
-#include <dt-bindings/clock/qcom,sa8775p-gpucc.h>
+#include <dt-bindings/clock/qcom,qcs8300-gpucc.h>
 
 #include "clk-alpha-pll.h"
 #include "clk-branch.h"
@@ -317,6 +317,24 @@ static struct clk_branch gpu_cc_crc_ahb_clk = {
        },
 };
 
+static struct clk_branch gpu_cc_cx_accu_shift_clk = {
+       .halt_reg = 0x95e8,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x95e8,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data){
+                       .name = "gpu_cc_cx_accu_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &gpu_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gpu_cc_cx_ff_clk = {
        .halt_reg = 0x914c,
        .halt_check = BRANCH_HALT,
@@ -420,6 +438,24 @@ static struct clk_branch gpu_cc_demet_clk = {
        },
 };
 
+static struct clk_branch gpu_cc_gx_accu_shift_clk = {
+       .halt_reg = 0x95e4,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x95e4,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data){
+                       .name = "gpu_cc_gx_accu_shift_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &gpu_cc_xo_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = {
        .halt_reg = 0x7000,
        .halt_check = BRANCH_HALT_VOTED,
@@ -499,6 +535,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
        [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
        [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr,
        [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
+       [GPU_CC_CX_ACCU_SHIFT_CLK] = NULL,
        [GPU_CC_CX_FF_CLK] = &gpu_cc_cx_ff_clk.clkr,
        [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
        [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
@@ -508,6 +545,7 @@ static struct clk_regmap *gpu_cc_sa8775p_clocks[] = {
        [GPU_CC_DEMET_DIV_CLK_SRC] = &gpu_cc_demet_div_clk_src.clkr,
        [GPU_CC_FF_CLK_SRC] = &gpu_cc_ff_clk_src.clkr,
        [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
+       [GPU_CC_GX_ACCU_SHIFT_CLK] = NULL,
        [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr,
        [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr,
        [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr,
@@ -583,6 +621,7 @@ static const struct qcom_cc_desc gpu_cc_sa8775p_desc = {
 };
 
 static const struct of_device_id gpu_cc_sa8775p_match_table[] = {
+       { .compatible = "qcom,qcs8300-gpucc" },
        { .compatible = "qcom,sa8775p-gpucc" },
        { }
 };
@@ -596,6 +635,14 @@ static int gpu_cc_sa8775p_probe(struct platform_device *pdev)
        if (IS_ERR(regmap))
                return PTR_ERR(regmap);
 
+       if (of_device_is_compatible(pdev->dev.of_node, "qcom,qcs8300-gpucc")) {
+               gpu_cc_pll0_config.l = 0x31;
+               gpu_cc_pll0_config.alpha = 0xe555;
+
+               gpu_cc_sa8775p_clocks[GPU_CC_CX_ACCU_SHIFT_CLK] = &gpu_cc_cx_accu_shift_clk.clkr;
+               gpu_cc_sa8775p_clocks[GPU_CC_GX_ACCU_SHIFT_CLK] = &gpu_cc_gx_accu_shift_clk.clkr;
+       }
+
        clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
        clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);