pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_U1_AGG_BUF_SIZE, &rxAggSize);
/* real update aggregation setting */
pBtCoexist->fBtcSet(pBtCoexist, BTC_SET_ACT_AGGREGATE_CTRL, NULL);
-
-
}
static void halbtc8723b1ant_QueryBtInfo(struct btc_coexist *pBtCoexist)
}
}
-
static void halbtc8723b1ant_MonitorWiFiCtr(struct btc_coexist *pBtCoexist)
{
s32 wifiRssi = 0;
pCoexSta->nCRCErr_11nAgg = pBtCoexist->fBtcRead2Byte(pBtCoexist, 0xfba);
}
-
/* reset counter */
pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x1);
pBtCoexist->fBtcWrite1ByteBitMask(pBtCoexist, 0xf16, 0x1, 0x0);
}
pCoexSta->bPreCCKLock = pCoexSta->bCCKLock;
-
-
}
static bool halbtc8723b1ant_IsWifiStatusChanged(struct btc_coexist *pBtCoexist)
}
}
-
/* ext switch setting */
switch (antPosType) {
case BTC_ANT_PATH_WIFI:
}
}
-
/* internal switch setting */
switch (antPosType) {
case BTC_ANT_PATH_WIFI:
pBtCoexist->fBtcFillH2c(pBtCoexist, 0x60, 5, H2C_Parameter);
}
-
static void halbtc8723b1ant_PsTdma(
struct btc_coexist *pBtCoexist, bool bForceExec, bool bTurnOn, u8 type
)
psTdmaByte4Val = 0x10; /* 0x778 = d/1 toggle */
}
-
if (bTurnOn) {
if (pBtLinkInfo->bSlaveRole)
psTdmaByte4Val = psTdmaByte4Val | 0x1; /* 0x778 = 0x1 at wifi slot (no blocking BT Low-Pri pkts) */
-
switch (type) {
default:
halbtc8723b1ant_SetFwPstdma(
return bCommon;
}
-
static void halbtc8723b1ant_TdmaDurationAdjustForAcl(
struct btc_coexist *pBtCoexist, u8 wifiStatus
)
return;
}
-
if (!bWifiConnected) {
bool bScan = false, bLink = false, bRoam = false;
/* 3 Tx Power Tracking */
/* 3 ============================================================ */
-
static void setIqkMatrix_8723B(
struct dm_odm_t *pDM_Odm,
u8 OFDM_index,
}
}
-
static void setCCKFilterCoefficient(struct dm_odm_t *pDM_Odm, u8 CCKSwingIndex)
{
u8 (*swingtable)[8];
}
}
-
void ConfigureTxpowerTrack_8723B(struct txpwrtrack_cfg *pConfig)
{
pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;
/* leave IQK mode */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
-
/* Check failed */
regEAC = PHY_QueryBBReg(pDM_Odm->Adapter, rRx_Power_After_IQK_A_2, bMaskDWord);
regE94 = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_Before_IQK_A, bMaskDWord);
regE9C = PHY_QueryBBReg(pDM_Odm->Adapter, rTx_Power_After_IQK_A, bMaskDWord);
-
/* Allen 20131125 */
tmp = (regE9C & 0x03FF0000)>>16;
if ((tmp & 0x200) > 0)
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0xf80);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x55, bRFRegOffsetMask, 0x4021f);
-
/* IQK setting */
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fc1);
-
-
/* 1 Tx IQK */
/* IQK setting */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0xed, 0x20, 0x1);
PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_A, 0x43, bRFRegOffsetMask, 0x30fcd);
-
/* IQK setting */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK, bMaskDWord, 0x01007c00);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK, bMaskDWord, 0x01004800);
-
/* path-B IQK setting */
PHY_SetBBReg(pDM_Odm->Adapter, rTx_IQK_Tone_A, bMaskDWord, 0x18008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rRx_IQK_Tone_A, bMaskDWord, 0x38008c1c);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
PHY_SetBBReg(pDM_Odm->Adapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
-
/* delay x ms */
/* PlatformStallExecution(IQK_DELAY_TIME_88E*1000); */
mdelay(IQK_DELAY_TIME_8723B);
/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, 0xffffff00, 0x00000000); */
/* PHY_SetRFReg(pDM_Odm->Adapter, RF_PATH_B, 0xdf, bRFRegOffsetMask, 0x180); */
-
-
/* Allen 20131125 */
tmp = (regEAC & 0x03FF0000)>>16;
if ((tmp & 0x200) > 0)
}
}
-
static void _PHY_SaveMACRegisters8723B(
struct adapter *padapter, u32 *MACReg, u32 *MACBackup
)
}
-
static void _PHY_ReloadADDARegisters8723B(
struct adapter *padapter,
u32 *ADDAReg,
rtw_write32(padapter, MACReg[i], MACBackup[i]);
}
-
static void _PHY_PathADDAOn8723B(
struct adapter *padapter,
u32 *ADDAReg,
}
}
-
-
static void phy_IQCalibrate_8723B(
struct adapter *padapter,
s32 result[][8],
PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
-
/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01); */
/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01); */
/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00); */
/* PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00); */
-
/* RX IQ calibration setting for 8723B D cut large current issue when leaving IPS */
PHY_SetBBReg(pDM_Odm->Adapter, rFPGA0_IQK, bMaskH3Bytes, 0x000000);
}
-
static void phy_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm, bool is2T)
{
u8 tmpReg;
if (pDM_Odm->RFCalibrateInfo.bIQKInProgress)
return;
-
pDM_Odm->RFCalibrateInfo.bIQKInProgress = true;
if (bRestore) {
/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT12, 0x0); */
/* PHY_SetBBReg(pDM_Odm->Adapter, 0x764, BIT11, 0x1); */
-
for (i = 0; i < 8; i++) {
result[0][i] = 0;
result[1][i] = 0;
is23simular = false;
is13simular = false;
-
for (i = 0; i < 3; i++) {
phy_IQCalibrate_8723B(padapter, result, i, Is2ant, RF_Path);
pDM_Odm->RFCalibrateInfo.bIQKInProgress = false;
}
-
void PHY_LCCalibrate_8723B(struct dm_odm_t *pDM_Odm)
{
bool bSingleTone = false, bCarrierSuppression = false;
pDM_Odm->RFCalibrateInfo.bLCKInProgress = true;
-
phy_LCCalibrate_8723B(pDM_Odm, false);
-
pDM_Odm->RFCalibrateInfo.bLCKInProgress = false;
}