backport: re PR target/79568 (ICE in extract_insn, at recog.c:2311 for pr70325.c...

	Backported from mainline
	2017-02-20  Jakub Jelinek  <jakub@redhat.com>

	PR target/79568
	* config/i386/i386.c (ix86_expand_builtin): Handle
	OPTION_MASK_ISA_AVX512VL and OPTION_MASK_ISA_64BIT in
	ix86_builtins_isa[fcode].isa as a requirement of those
	flags and any other flag in the bitmask.
	(ix86_init_mmx_sse_builtins): Use 0 instead of
	~OPTION_MASK_ISA_64BIT as mask.
	* config/i386/i386-builtin.def (bdesc_special_args,
	bdesc_args): Likewise.

	* gcc.target/i386/pr79568-1.c: New test.
	* gcc.target/i386/pr79568-2.c: New test.
	* gcc.target/i386/pr79568-3.c: New test.

From-SVN: r248645

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index fc6155647c52a4ddb0118f1cb32996137bd0e825..b4d09b55d8dd5862c2c1ca60cbc05c20089da98c 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,6 +1,18 @@
 2017-05-30  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline
+       2017-02-20  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/79568
+       * config/i386/i386.c (ix86_expand_builtin): Handle
+       OPTION_MASK_ISA_AVX512VL and OPTION_MASK_ISA_64BIT in
+       ix86_builtins_isa[fcode].isa as a requirement of those
+       flags and any other flag in the bitmask.
+       (ix86_init_mmx_sse_builtins): Use 0 instead of
+       ~OPTION_MASK_ISA_64BIT as mask.
+       * config/i386/i386-builtin.def (bdesc_special_args,
+       bdesc_args): Likewise.
+
        2017-02-18  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/79559

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ae3aa226b754ce5e057c0badb55054bc16a63dba..d9268c32673774d0ad101018b062a64f11c52c61 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -31012,9 +31012,9 @@ static const struct builtin_description bdesc_pcmpistr[] =
 /* Special builtins with variable number of arguments.  */
 static const struct builtin_description bdesc_special_args[] =
 {
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
+  { 0, CODE_FOR_nothing, "__builtin_ia32_rdtsc", IX86_BUILTIN_RDTSC, UNKNOWN, (int) UINT64_FTYPE_VOID },
+  { 0, CODE_FOR_nothing, "__builtin_ia32_rdtscp", IX86_BUILTIN_RDTSCP, UNKNOWN, (int) UINT64_FTYPE_PUNSIGNED },
+  { 0, CODE_FOR_pause, "__builtin_ia32_pause", IX86_BUILTIN_PAUSE, UNKNOWN, (int) VOID_FTYPE_VOID },
 
   /* 80387 (for use internally for atomic compound assignment).  */
   { 0, CODE_FOR_fnstenv, "__builtin_ia32_fnstenv", IX86_BUILTIN_FNSTENV, UNKNOWN, (int) VOID_FTYPE_PVOID },
@@ -31305,13 +31305,13 @@ static const struct builtin_description bdesc_special_args[] =
 /* Builtins with variable number of arguments.  */
 static const struct builtin_description bdesc_args[] =
 {
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
+  { 0, CODE_FOR_bsr, "__builtin_ia32_bsrsi", IX86_BUILTIN_BSRSI, UNKNOWN, (int) INT_FTYPE_INT },
   { OPTION_MASK_ISA_64BIT, CODE_FOR_bsr_rex64, "__builtin_ia32_bsrdi", IX86_BUILTIN_BSRDI, UNKNOWN, (int) INT64_FTYPE_INT64 },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
-  { ~OPTION_MASK_ISA_64BIT, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
+  { 0, CODE_FOR_nothing, "__builtin_ia32_rdpmc", IX86_BUILTIN_RDPMC, UNKNOWN, (int) UINT64_FTYPE_INT },
+  { 0, CODE_FOR_rotlqi3, "__builtin_ia32_rolqi", IX86_BUILTIN_ROLQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
+  { 0, CODE_FOR_rotlhi3, "__builtin_ia32_rolhi", IX86_BUILTIN_ROLHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
+  { 0, CODE_FOR_rotrqi3, "__builtin_ia32_rorqi", IX86_BUILTIN_RORQI, UNKNOWN, (int) UINT8_FTYPE_UINT8_INT },
+  { 0, CODE_FOR_rotrhi3, "__builtin_ia32_rorhi", IX86_BUILTIN_RORHI, UNKNOWN, (int) UINT16_FTYPE_UINT16_INT },
 
   /* MMX */
   { OPTION_MASK_ISA_MMX, CODE_FOR_mmx_addv8qi3, "__builtin_ia32_paddb", IX86_BUILTIN_PADDB, UNKNOWN, (int) V8QI_FTYPE_V8QI_V8QI },
@@ -34384,11 +34384,11 @@ ix86_init_mmx_sse_builtins (void)
               IX86_BUILTIN_SBB64);
 
   /* Read/write FLAGS.  */
-  def_builtin (~OPTION_MASK_ISA_64BIT, "__builtin_ia32_readeflags_u32",
+  def_builtin (0, "__builtin_ia32_readeflags_u32",
                UNSIGNED_FTYPE_VOID, IX86_BUILTIN_READ_FLAGS);
   def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_ia32_readeflags_u64",
                UINT64_FTYPE_VOID, IX86_BUILTIN_READ_FLAGS);
-  def_builtin (~OPTION_MASK_ISA_64BIT, "__builtin_ia32_writeeflags_u32",
+  def_builtin (0, "__builtin_ia32_writeeflags_u32",
                VOID_FTYPE_UNSIGNED, IX86_BUILTIN_WRITE_FLAGS);
   def_builtin (OPTION_MASK_ISA_64BIT, "__builtin_ia32_writeeflags_u64",
                VOID_FTYPE_UINT64, IX86_BUILTIN_WRITE_FLAGS);
@@ -38750,9 +38750,18 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
      Originally the builtin was not created if it wasn't applicable to the
      current ISA based on the command line switches.  With function specific
      options, we need to check in the context of the function making the call
-     whether it is supported.  */
-  if (ix86_builtins_isa[fcode].isa
-      && !(ix86_builtins_isa[fcode].isa & ix86_isa_flags))
+     whether it is supported.  Treat AVX512VL specially.  For other flags,
+     if isa includes more than one ISA bit, treat those are requiring any
+     of them.  For AVX512VL, require both AVX512VL and the non-AVX512VL
+     ISAs.  Similarly for 64BIT, but we shouldn't be building such builtins
+     at all, -m64 is a whole TU option.  */
+  if (((ix86_builtins_isa[fcode].isa
+       & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT))
+       && !(ix86_builtins_isa[fcode].isa
+           & ~(OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_64BIT)
+           & ix86_isa_flags))
+      || ((ix86_builtins_isa[fcode].isa & OPTION_MASK_ISA_AVX512VL)
+         && !(ix86_isa_flags & OPTION_MASK_ISA_AVX512VL)))
     {
       char *opts = ix86_target_string (ix86_builtins_isa[fcode].isa, 0, NULL,
                                       NULL, (enum fpmath_unit) 0, false);

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 826a35d61197eb1721c0f38472972487e8399722..8a6d56b515c3cc2b51fd996efa43bdbe45c3e9d4 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,6 +1,13 @@
 2017-05-30  Jakub Jelinek  <jakub@redhat.com>
 
        Backported from mainline
+       2017-02-20  Jakub Jelinek  <jakub@redhat.com>
+
+       PR target/79568
+       * gcc.target/i386/pr79568-1.c: New test.
+       * gcc.target/i386/pr79568-2.c: New test.
+       * gcc.target/i386/pr79568-3.c: New test.
+
        2017-02-18  Jakub Jelinek  <jakub@redhat.com>
 
        PR target/79559

diff --git a/gcc/testsuite/gcc.target/i386/pr79568-1.c b/gcc/testsuite/gcc.target/i386/pr79568-1.c
new file mode 100644 (file)
index 0000000..3bda3b5
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-1.c
@@ -0,0 +1,18 @@
+/* PR target/79568 */
+/* { dg-do compile } */
+/* { dg-options "-mno-avx512vl -mavx512bw -O2" } */
+
+#pragma GCC push_options
+#pragma GCC target ("avx512vl,avx512bw")
+void
+foo (char __attribute__ ((__vector_size__(32))) *x, char __attribute__ ((__vector_size__(32))) *y, int z)
+{
+  __builtin_ia32_storedquqi256_mask (x, *y, z);
+}
+#pragma GCC pop_options
+
+void
+bar (char __attribute__ ((__vector_size__(32))) *x, char __attribute__ ((__vector_size__(32))) *y, int z)
+{
+  __builtin_ia32_storedquqi256_mask (x, *y, z); /* { dg-error "needs isa option" } */
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr79568-2.c b/gcc/testsuite/gcc.target/i386/pr79568-2.c
new file mode 100644 (file)
index 0000000..a0ee8e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-2.c
@@ -0,0 +1,18 @@
+/* PR target/79568 */
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-mno-lwp" } */
+
+#pragma GCC push_options
+#pragma GCC target ("lwp")
+void
+foo (unsigned long x, unsigned int y)
+{
+  __builtin_ia32_lwpval64 (x, y, 1);
+}
+#pragma GCC pop_options
+
+void
+bar (unsigned long x, unsigned int y)
+{
+  __builtin_ia32_lwpval64 (x, y, 1);    /* { dg-error "needs isa option" } */
+}

diff --git a/gcc/testsuite/gcc.target/i386/pr79568-3.c b/gcc/testsuite/gcc.target/i386/pr79568-3.c
new file mode 100644 (file)
index 0000000..c210162
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr79568-3.c
@@ -0,0 +1,19 @@
+/* PR target/79568 */
+/* { dg-do compile } */
+/* { dg-options "-mno-sahf -mno-mmx -mno-sse" } */
+/* { dg-additional-options "-march=i386" { target ia32 } } */
+
+#pragma GCC push_options
+#pragma GCC target ("sse")
+void
+foo (void)
+{
+  __builtin_ia32_pause ();
+}
+#pragma GCC pop_options
+
+void
+bar (void)
+{
+  __builtin_ia32_pause ();
+}