*/
#define QUADSPI_QUIRK_USE_TDH_SETTING BIT(5)
+/*
+ * Do not disable the "qspi" clock when changing its rate.
+ */
+#define QUADSPI_QUIRK_SKIP_CLK_DISABLE BIT(6)
+
struct fsl_qspi_devtype_data {
unsigned int rxfifo;
unsigned int txfifo;
return !!(q->devtype_data->quirks & QUADSPI_QUIRK_USE_TDH_SETTING);
}
+static bool needs_clk_disable(struct fsl_qspi *q)
+{
+ return !(q->devtype_data->quirks & QUADSPI_QUIRK_SKIP_CLK_DISABLE);
+}
+
/*
* An IC bug makes it necessary to rearrange the 32-bit data.
* Later chips, such as IMX6SLX, have fixed this bug.
if (needs_4x_clock(q))
rate *= 4;
- fsl_qspi_clk_disable_unprep(q);
+ if (needs_clk_disable(q))
+ fsl_qspi_clk_disable_unprep(q);
ret = clk_set_rate(q->clk, rate);
if (ret)
return;
- ret = fsl_qspi_clk_prep_enable(q);
- if (ret)
- return;
+ if (needs_clk_disable(q)) {
+ ret = fsl_qspi_clk_prep_enable(q);
+ if (ret)
+ return;
+ }
q->selected = spi_get_chipselect(spi, 0);