{ PCI_DEVICE_DATA(INTEL, NPK_ADL_P, &intel_th_2x) }, /* Alder Lake-P */
{ PCI_DEVICE_DATA(INTEL, NPK_ADL_M, &intel_th_2x) }, /* Alder Lake-M */
{ PCI_DEVICE_DATA(INTEL, NPK_APL, NULL) }, /* Apollo Lake */
+ { PCI_DEVICE_DATA(INTEL, NPK_NVL_PCH, &intel_th_2x) }, /* Nova Lake-PCH */
{ PCI_DEVICE_DATA(INTEL, NPK_ARL, &intel_th_2x) }, /* Arrow Lake */
{ PCI_DEVICE_DATA(INTEL, NPK_RPL_S, &intel_th_2x) }, /* Raptor Lake-S */
{ PCI_DEVICE_DATA(INTEL, NPK_ADL, &intel_th_2x) }, /* Alder Lake */
{ PCI_DEVICE_DATA(INTEL, NPK_RPL_S_CPU, &intel_th_2x) }, /* Raptor Lake-S CPU */
{ PCI_DEVICE_DATA(INTEL, NPK_LNL, &intel_th_2x) }, /* Lunar Lake */
{ PCI_DEVICE_DATA(INTEL, NPK_MTL_S_CPU, &intel_th_2x) }, /* Meteor Lake-S CPU */
+ { PCI_DEVICE_DATA(INTEL, NPK_NVL_P, &intel_th_2x) }, /* Nova Lake-P */
+ { PCI_DEVICE_DATA(INTEL, NPK_NVL_H, &intel_th_2x) }, /* Nova Lake-H */
+ { PCI_DEVICE_DATA(INTEL, NPK_NVL_S, &intel_th_2x) }, /* Nova Lake-S */
{ PCI_DEVICE_DATA(INTEL, NPK_PTL_H, &intel_th_2x) }, /* Panther Lake-H */
{ PCI_DEVICE_DATA(INTEL, NPK_PTL_PU, &intel_th_2x) }, /* Panther Lake-P/U */
{ }
#define PCI_DEVICE_ID_INTEL_NPK_ADL_P 0x51a6
#define PCI_DEVICE_ID_INTEL_NPK_ADL_M 0x54a6
#define PCI_DEVICE_ID_INTEL_NPK_APL 0x5a8e
+#define PCI_DEVICE_ID_INTEL_NPK_NVL_PCH 0x6e26
#define PCI_DEVICE_ID_INTEL_NPK_ARL 0x7724
#define PCI_DEVICE_ID_INTEL_NPK_RPL_S 0x7a26
#define PCI_DEVICE_ID_INTEL_NPK_ADL 0x7aa6
#define PCI_DEVICE_ID_INTEL_NPK_RPL_S_CPU 0xa76f
#define PCI_DEVICE_ID_INTEL_NPK_LNL 0xa824
#define PCI_DEVICE_ID_INTEL_NPK_MTL_S_CPU 0xae24
+#define PCI_DEVICE_ID_INTEL_NPK_NVL_P 0xd224
+#define PCI_DEVICE_ID_INTEL_NPK_NVL_H 0xd324
+#define PCI_DEVICE_ID_INTEL_NPK_NVL_S 0xd424
#define PCI_DEVICE_ID_INTEL_NPK_PTL_H 0xe324
#define PCI_DEVICE_ID_INTEL_NPK_PTL_PU 0xe424