media: qcom: camss: Add x1e80100 specific support

Populate CAMSS with x1e80100 specific hooks.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bryan O'Donoghue <bod@kernel.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>

diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index d5f717f6215c45908c4fc5a8650d68c00d544db7..f732a76de93e3e7b787d9553bf7f31e6c0596c58 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -749,6 +749,7 @@ static bool csiphy_is_gen2(u32 version)
        case CAMSS_8280XP:
        case CAMSS_845:
        case CAMSS_8550:
+       case CAMSS_X1E80100:
                ret = true;
                break;
        }
@@ -837,6 +838,11 @@ static int csiphy_init(struct csiphy_device *csiphy)
                regs->lane_regs = &lane_regs_sc8280xp[0];
                regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
                break;
+       case CAMSS_X1E80100:
+               regs->lane_regs = &lane_regs_x1e80100[0];
+               regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+               regs->offset = 0x1000;
+               break;
        case CAMSS_8550:
                regs->lane_regs = &lane_regs_sm8550[0];
                regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);

diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c
index 91bc0cb7781e44625425ea880465cea7ce041016..4bca6c3abaff9b898ea879674a3ff8f3592d3139 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss-vfe.c
+++ b/drivers/media/platform/qcom/camss/camss-vfe.c
@@ -346,6 +346,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code,
        case CAMSS_8280XP:
        case CAMSS_845:
        case CAMSS_8550:
+       case CAMSS_X1E80100:
                switch (sink_code) {
                case MEDIA_BUS_FMT_YUYV8_1X16:
                {
@@ -1973,6 +1974,7 @@ static int vfe_bpl_align(struct vfe_device *vfe)
        case CAMSS_8280XP:
        case CAMSS_845:
        case CAMSS_8550:
+       case CAMSS_X1E80100:
                ret = 16;
                break;
        default:

diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c
index d7e0e802852a22d0e2dd849c50be6c4c58e19f38..06f42875702f02f9d8d83d06ddaa972eacb593f8 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss.c
+++ b/drivers/media/platform/qcom/camss/camss.c
@@ -2483,6 +2483,299 @@ static const struct resources_icc icc_res_sm8550[] = {
        },
 };
 
+static const struct camss_subdev_resources csiphy_res_x1e80100[] = {
+       /* CSIPHY0 */
+       {
+               .regulators = { "vdd-csiphy-0p8-supply",
+                               "vdd-csiphy-1p2-supply" },
+               .clock = { "csiphy0", "csiphy0_timer" },
+               .clock_rate = { { 300000000, 400000000, 480000000 },
+                               { 266666667, 400000000 } },
+               .reg = { "csiphy0" },
+               .interrupt = { "csiphy0" },
+               .csiphy = {
+                       .id = 0,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               },
+       },
+       /* CSIPHY1 */
+       {
+               .regulators = { "vdd-csiphy-0p8-supply",
+                               "vdd-csiphy-1p2-supply" },
+               .clock = { "csiphy1", "csiphy1_timer" },
+               .clock_rate = { { 300000000, 400000000, 480000000 },
+                               { 266666667, 400000000 } },
+               .reg = { "csiphy1" },
+               .interrupt = { "csiphy1" },
+               .csiphy = {
+                       .id = 1,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               },
+       },
+       /* CSIPHY2 */
+       {
+               .regulators = { "vdd-csiphy-0p8-supply",
+                               "vdd-csiphy-1p2-supply" },
+               .clock = { "csiphy2", "csiphy2_timer" },
+               .clock_rate = { { 300000000, 400000000, 480000000 },
+                               { 266666667, 400000000 } },
+               .reg = { "csiphy2" },
+               .interrupt = { "csiphy2" },
+               .csiphy = {
+                       .id = 2,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               },
+       },
+       /* CSIPHY4 */
+       {
+               .regulators = { "vdd-csiphy-0p8-supply",
+                               "vdd-csiphy-1p2-supply" },
+               .clock = { "csiphy4", "csiphy4_timer" },
+               .clock_rate = { { 300000000, 400000000, 480000000 },
+                               { 266666667, 400000000 } },
+               .reg = { "csiphy4" },
+               .interrupt = { "csiphy4" },
+               .csiphy = {
+                       .id = 4,
+                       .hw_ops = &csiphy_ops_3ph_1_0,
+                       .formats = &csiphy_formats_sdm845
+               },
+       },
+};
+
+static const struct camss_subdev_resources csid_res_x1e80100[] = {
+       /* CSID0 */
+       {
+               .regulators = {},
+               .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
+                          "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 64000000, 80000000 },
+                               { 80000000,  100000000, 200000000,
+                                 300000000, 400000000 },
+                               { 300000000, 400000000, 480000000 },
+                               { 300000000, 400000000, 480000000 }, },
+               .reg = { "csid0" },
+               .interrupt = { "csid0" },
+               .csid = {
+                       .hw_ops = &csid_ops_680,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               },
+       },
+       /* CSID1 */
+       {
+               .regulators = {},
+               .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
+                          "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 64000000, 80000000 },
+                               { 80000000,  100000000, 200000000,
+                                 300000000, 400000000 },
+                               { 300000000, 400000000, 480000000 },
+                               { 300000000, 400000000, 480000000 }, },
+               .reg = { "csid1" },
+               .interrupt = { "csid1" },
+               .csid = {
+                       .hw_ops = &csid_ops_680,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               },
+       },
+       /* CSID2 */
+       {
+               .regulators = {},
+               .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
+                          "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 64000000, 80000000 },
+                               { 80000000,  100000000, 200000000,
+                                 300000000, 400000000 },
+                               { 300000000, 400000000, 480000000 },
+                               { 300000000, 400000000, 480000000 }, },
+               .reg = { "csid2" },
+               .interrupt = { "csid2" },
+               .csid = {
+                       .hw_ops = &csid_ops_680,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               },
+       },
+       /* CSID_LITE0 */
+       {
+               .regulators = {},
+               .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
+                          "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 64000000, 80000000 },
+                               { 80000000,  100000000, 200000000,
+                                 300000000, 400000000 },
+                               { 300000000, 400000000, 480000000 },
+                               { 300000000, 400000000, 480000000 }, },
+               .reg = { "csid_lite0" },
+               .interrupt = { "csid_lite0" },
+               .csid = {
+                       .is_lite = true,
+                       .hw_ops = &csid_ops_680,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               }
+       },
+       /* CSID_LITE1 */
+       {
+               .regulators = {},
+               .clock = { "gcc_axi_hf", "gcc_axi_sf", "cpas_ahb",
+                          "cpas_fast_ahb", "csid", "csid_csiphy_rx" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 64000000, 80000000 },
+                               { 80000000,  100000000, 200000000,
+                                 300000000, 400000000 },
+                               { 300000000, 400000000, 480000000 },
+                               { 300000000, 400000000, 480000000 }, },
+
+               .reg = { "csid_lite1" },
+               .interrupt = { "csid_lite1" },
+               .csid = {
+                       .is_lite = true,
+                       .hw_ops = &csid_ops_680,
+                       .parent_dev_ops = &vfe_parent_dev_ops,
+                       .formats = &csid_formats_gen2
+               }
+       },
+};
+
+static const struct camss_subdev_resources vfe_res_x1e80100[] = {
+       /* IFE0 */
+       {
+               .regulators = {},
+               .clock = {"camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+                         "cpas_fast_ahb", "cpas_vfe0", "vfe0_fast_ahb",
+                         "vfe0" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 345600000, 432000000, 594000000, 675000000,
+                                 727000000 }, },
+               .reg = { "vfe0" },
+               .interrupt = { "vfe0" },
+               .vfe = {
+                       .line_num = 4,
+                       .pd_name = "ife0",
+                       .hw_ops = &vfe_ops_680,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* IFE1 */
+       {
+               .regulators = {},
+               .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+                          "cpas_fast_ahb", "cpas_vfe1", "vfe1_fast_ahb",
+                          "vfe1"  },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 345600000, 432000000, 594000000, 675000000,
+                                 727000000 }, },
+               .reg = { "vfe1" },
+               .interrupt = { "vfe1" },
+               .vfe = {
+                       .line_num = 4,
+                       .pd_name = "ife1",
+                       .hw_ops = &vfe_ops_680,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* IFE_LITE_0 */
+       {
+               .regulators = {},
+               .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+                          "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
+                          "vfe_lite_csid" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 266666667, 400000000, 480000000 },
+                               { 266666667, 400000000, 480000000 }, },
+               .reg = { "vfe_lite0" },
+               .interrupt = { "vfe_lite0" },
+               .vfe = {
+                       .is_lite = true,
+                       .line_num = 4,
+                       .hw_ops = &vfe_ops_680,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+       /* IFE_LITE_1 */
+       {
+               .regulators = {},
+               .clock = { "camnoc_rt_axi", "camnoc_nrt_axi", "cpas_ahb",
+                          "vfe_lite_ahb", "cpas_vfe_lite", "vfe_lite",
+                          "vfe_lite_csid" },
+               .clock_rate = { { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 0 },
+                               { 266666667, 400000000, 480000000 },
+                               { 266666667, 400000000, 480000000 }, },
+               .reg = { "vfe_lite1" },
+               .interrupt = { "vfe_lite1" },
+               .vfe = {
+                       .is_lite = true,
+                       .line_num = 4,
+                       .hw_ops = &vfe_ops_680,
+                       .formats_rdi = &vfe_formats_rdi_845,
+                       .formats_pix = &vfe_formats_pix_845
+               },
+       },
+};
+
+static const struct resources_icc icc_res_x1e80100[] = {
+       {
+               .name = "ahb",
+               .icc_bw_tbl.avg = 150000,
+               .icc_bw_tbl.peak = 300000,
+       },
+       {
+               .name = "hf_mnoc",
+               .icc_bw_tbl.avg = 2097152,
+               .icc_bw_tbl.peak = 2097152,
+       },
+       {
+               .name = "sf_mnoc",
+               .icc_bw_tbl.avg = 2097152,
+               .icc_bw_tbl.peak = 2097152,
+       },
+       {
+               .name = "sf_icp_mnoc",
+               .icc_bw_tbl.avg = 2097152,
+               .icc_bw_tbl.peak = 2097152,
+       },
+};
+
+static const struct resources_wrapper csid_wrapper_res_x1e80100 = {
+       .reg = "csid_wrapper",
+};
+
 /*
  * camss_add_clock_margin - Add margin to clock frequency rate
  * @rate: Clock frequency rate
@@ -3553,6 +3846,21 @@ static const struct camss_resources sm8550_resources = {
        .link_entities = camss_link_entities
 };
 
+static const struct camss_resources x1e80100_resources = {
+       .version = CAMSS_X1E80100,
+       .pd_name = "top",
+       .csiphy_res = csiphy_res_x1e80100,
+       .csid_res = csid_res_x1e80100,
+       .vfe_res = vfe_res_x1e80100,
+       .csid_wrapper_res = &csid_wrapper_res_x1e80100,
+       .icc_res = icc_res_x1e80100,
+       .icc_path_num = ARRAY_SIZE(icc_res_x1e80100),
+       .csiphy_num = ARRAY_SIZE(csiphy_res_x1e80100),
+       .csid_num = ARRAY_SIZE(csid_res_x1e80100),
+       .vfe_num = ARRAY_SIZE(vfe_res_x1e80100),
+       .link_entities = camss_link_entities
+};
+
 static const struct of_device_id camss_dt_match[] = {
        { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources },
        { .compatible = "qcom,msm8953-camss", .data = &msm8953_resources },
@@ -3564,6 +3872,7 @@ static const struct of_device_id camss_dt_match[] = {
        { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources },
        { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources },
        { .compatible = "qcom,sm8550-camss", .data = &sm8550_resources },
+       { .compatible = "qcom,x1e80100-camss", .data = &x1e80100_resources },
        { }
 };
 

diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h
index b284b910ce421c98df5e77f942f82486342bfcec..63c0afee154a02194820016ccf554620d6521c8b 100644 (file)
--- a/drivers/media/platform/qcom/camss/camss.h
+++ b/drivers/media/platform/qcom/camss/camss.h
@@ -86,6 +86,7 @@ enum camss_version {
        CAMSS_8280XP,
        CAMSS_845,
        CAMSS_8550,
+       CAMSS_X1E80100,
 };
 
 enum icc_count {