/* Convert one amd64 insn to IR. See the type DisOneInstrFn in
bb_to_IR.h. */
extern
-DisResult disInstr_AMD64 ( IRBB* irbb,
+DisResult disInstr_AMD64 ( IRSB* irbb,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian );
/* Used by the optimiser to specialise calls to helpers. */
translated. */
static Addr64 guest_RIP_curr_instr;
-/* The IRBB* into which we're generating code. */
-static IRBB* irbb;
+/* The IRSB* into which we're generating code. */
+static IRSB* irsb;
/* For ensuring that %rip-relative addressing is done right. A read
of %rip generates the address of the next instruction. It may be
static IRTemp newTemp ( IRType ty )
{
vassert(isPlausibleIRType(ty));
- return newIRTemp( irbb->tyenv, ty );
+ return newIRTemp( irsb->tyenv, ty );
}
-/* Add a statement to the list held by "irbb". */
+/* Add a statement to the list held by "irsb". */
static void stmt ( IRStmt* st )
{
- addStmtToIRBB( irbb, st );
+ addStmtToIRSB( irsb, st );
}
/* Generate a statement "dst := e". */
static void assign ( IRTemp dst, IRExpr* e )
{
- stmt( IRStmt_Tmp(dst, e) );
+ stmt( IRStmt_WrTmp(dst, e) );
}
static IRExpr* unop ( IROp op, IRExpr* a )
static IRExpr* mkexpr ( IRTemp tmp )
{
- return IRExpr_Tmp(tmp);
+ return IRExpr_RdTmp(tmp);
}
static IRExpr* mkU8 ( ULong i )
static void putIRegAH ( IRExpr* e )
{
vassert(!host_is_bigendian);
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
stmt( IRStmt_Put( OFFB_RAX+1, e ) );
}
static void putIRegRAX ( Int sz, IRExpr* e )
{
- IRType ty = typeOfIRExpr(irbb->tyenv, e);
+ IRType ty = typeOfIRExpr(irsb->tyenv, e);
vassert(!host_is_bigendian);
switch (sz) {
case 8: vassert(ty == Ity_I64);
static void putIRegRDX ( Int sz, IRExpr* e )
{
vassert(!host_is_bigendian);
- vassert(typeOfIRExpr(irbb->tyenv, e) == szToITy(sz));
+ vassert(typeOfIRExpr(irsb->tyenv, e) == szToITy(sz));
switch (sz) {
case 8: stmt( IRStmt_Put( OFFB_RDX, e ));
break;
static void putIReg64 ( UInt regno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
stmt( IRStmt_Put( integerGuestReg64Offset(regno), e ) );
}
static void putIReg32 ( UInt regno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32);
stmt( IRStmt_Put( integerGuestReg64Offset(regno),
unop(Iop_32Uto64,e) ) );
}
vassert(lo3bits < 8);
vassert(IS_VALID_PFX(pfx));
vassert(sz == 8 || sz == 4 || sz == 2 || sz == 1);
- vassert(typeOfIRExpr(irbb->tyenv, e) == szToITy(sz));
+ vassert(typeOfIRExpr(irsb->tyenv, e) == szToITy(sz));
stmt( IRStmt_Put(
offsetIReg( sz, lo3bits | (getRexB(pfx) << 3),
toBool(sz==1 && !haveREX(pfx)) ),
static
void putIRegG ( Int sz, Prefix pfx, UChar mod_reg_rm, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == szToITy(sz));
+ vassert(typeOfIRExpr(irsb->tyenv,e) == szToITy(sz));
if (sz == 4) {
e = unop(Iop_32Uto64,e);
}
static
void putIRegE ( Int sz, Prefix pfx, UChar mod_reg_rm, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == szToITy(sz));
+ vassert(typeOfIRExpr(irsb->tyenv,e) == szToITy(sz));
if (sz == 4) {
e = unop(Iop_32Uto64,e);
}
//..
//.. static void putSReg ( UInt sreg, IRExpr* e )
//.. {
-//.. vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I16);
+//.. vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
//.. stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) );
//.. }
static void putXMMReg ( UInt xmmreg, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128);
stmt( IRStmt_Put( xmmGuestRegOffset(xmmreg), e ) );
}
static void putXMMRegLane64 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane64F ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_F64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F64);
stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane32F ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_F32);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F32);
stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane32 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32);
stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane16 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I16);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
stmt( IRStmt_Put( xmmGuestRegLane16offset(xmmreg,laneno), e ) );
}
static IRExpr* mkAnd1 ( IRExpr* x, IRExpr* y )
{
- vassert(typeOfIRExpr(irbb->tyenv,x) == Ity_I1);
- vassert(typeOfIRExpr(irbb->tyenv,y) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv,x) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv,y) == Ity_I1);
return unop(Iop_64to1,
binop(Iop_And64,
unop(Iop_1Uto64,x),
/* U-widen 8/16/32/64 bit int expr to 64. */
static IRExpr* widenUto64 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I64: return e;
case Ity_I32: return unop(Iop_32Uto64, e);
case Ity_I16: return unop(Iop_16Uto64, e);
/* S-widen 8/16/32/64 bit int expr to 32. */
static IRExpr* widenSto64 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I64: return e;
case Ity_I32: return unop(Iop_32Sto64, e);
case Ity_I16: return unop(Iop_16Sto64, e);
of these combinations make sense. */
static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e )
{
- IRType src_ty = typeOfIRExpr(irbb->tyenv,e);
+ IRType src_ty = typeOfIRExpr(irsb->tyenv,e);
if (src_ty == dst_ty)
return e;
if (src_ty == Ity_I32 && dst_ty == Ity_I16)
static void jmp_lit( IRJumpKind kind, Addr64 d64 )
{
- irbb->next = mkU64(d64);
- irbb->jumpkind = kind;
+ irsb->next = mkU64(d64);
+ irsb->jumpkind = kind;
}
static void jmp_treg( IRJumpKind kind, IRTemp t )
{
- irbb->next = mkexpr(t);
- irbb->jumpkind = kind;
+ irsb->next = mkexpr(t);
+ irsb->jumpkind = kind;
}
static
stmt( IRStmt_Exit( mk_amd64g_calculate_condition(condPos),
Ijk_Boring,
IRConst_U64(d64_false) ) );
- irbb->next = mkU64(d64_true);
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkU64(d64_true);
+ irsb->jumpkind = Ijk_Boring;
} else {
stmt( IRStmt_Exit( mk_amd64g_calculate_condition(condPos),
Ijk_Boring,
IRConst_U64(d64_true) ) );
- irbb->next = mkU64(d64_false);
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkU64(d64_false);
+ irsb->jumpkind = Ijk_Boring;
}
}
be regarded as uninitialised.
*/
static
-void make_redzone_AbiHint ( VexMiscInfo* vmi, IRTemp new_rsp, HChar* who )
+void make_redzone_AbiHint ( VexAbiInfo* vbi, IRTemp new_rsp, HChar* who )
{
- Int szB = vmi->guest_stack_redzone_size;
+ Int szB = vbi->guest_stack_redzone_size;
vassert(szB >= 0);
/* A bit of a kludge. Currently the only AbI we've guested AMD64
vassert(szB == 128);
if (0) vex_printf("AbiHint: %s\n", who);
- vassert(typeOfIRTemp(irbb->tyenv, new_rsp) == Ity_I64);
+ vassert(typeOfIRTemp(irsb->tyenv, new_rsp) == Ity_I64);
if (szB > 0)
stmt( IRStmt_AbiHint(
binop(Iop_Sub64, mkexpr(new_rsp), mkU64(szB)),
/* Group 5 extended opcodes. */
static
-ULong dis_Grp5 ( VexMiscInfo* vmi,
+ULong dis_Grp5 ( VexAbiInfo* vbi,
Prefix pfx, Int sz, Long delta, DisResult* dres )
{
Int len;
assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
putIReg64(R_RSP, mkexpr(t2));
storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta+1));
- make_redzone_AbiHint(vmi, t2, "call-Ev(reg)");
+ make_redzone_AbiHint(vbi, t2, "call-Ev(reg)");
jmp_treg(Ijk_Call,t3);
dres->whatNext = Dis_StopHere;
showSz = False;
assign(t2, binop(Iop_Sub64, getIReg64(R_RSP), mkU64(8)));
putIReg64(R_RSP, mkexpr(t2));
storeLE( mkexpr(t2), mkU64(guest_RIP_bbstart+delta+len));
- make_redzone_AbiHint(vmi, t2, "call-Ev(mem)");
+ make_redzone_AbiHint(vbi, t2, "call-Ev(mem)");
jmp_treg(Ijk_Call,t3);
dres->whatNext = Dis_StopHere;
showSz = False;
static void put_emwarn ( IRExpr* e /* :: Ity_I32 */ )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
stmt( IRStmt_Put( OFFB_EMWARN, e ) );
}
static void put_ftop ( IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
stmt( IRStmt_Put( OFFB_FTOP, e ) );
}
static void put_C3210 ( IRExpr* e /* :: Ity_I64 */ )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I64);
stmt( IRStmt_Put( OFFB_FC3210, e ) );
}
static void put_fpround ( IRExpr* /* :: Ity_I32 */ e )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
stmt( IRStmt_Put( OFFB_FPROUND, unop(Iop_32Uto64,e) ) );
}
static void put_ST_TAG ( Int i, IRExpr* value )
{
- IRArray* descr;
- vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_I8);
- descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRRegArray* descr;
+ vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8);
+ descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
}
static IRExpr* get_ST_TAG ( Int i )
{
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
return IRExpr_GetI( descr, get_ftop(), i );
}
static void put_ST_UNCHECKED ( Int i, IRExpr* value )
{
- IRArray* descr;
- vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_F64);
- descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
+ IRRegArray* descr;
+ vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64);
+ descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
/* Mark the register as in-use. */
put_ST_TAG(i, mkU8(1));
static IRExpr* get_ST_UNCHECKED ( Int i )
{
- IRArray* descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
+ IRRegArray* descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
return IRExpr_GetI( descr, get_ftop(), i );
}
case 7: { /* FNSTSW m16 */
IRExpr* sw = get_FPU_sw();
- vassert(typeOfIRExpr(irbb->tyenv, sw) == Ity_I16);
+ vassert(typeOfIRExpr(irsb->tyenv, sw) == Ity_I16);
storeLE( mkexpr(addr), sw );
DIP("fnstsw %s\n", dis_buf);
break;
static void do_MMX_preamble ( void )
{
- Int i;
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
- IRExpr* zero = mkU32(0);
- IRExpr* tag1 = mkU8(1);
+ Int i;
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero = mkU32(0);
+ IRExpr* tag1 = mkU8(1);
put_ftop(zero);
for (i = 0; i < 8; i++)
stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
static void do_EMMS_preamble ( void )
{
- Int i;
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
- IRExpr* zero = mkU32(0);
- IRExpr* tag0 = mkU8(0);
+ Int i;
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero = mkU32(0);
+ IRExpr* tag0 = mkU8(0);
put_ftop(zero);
for (i = 0; i < 8; i++)
stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
static void putMMXReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 8);
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) );
}
//.. }
static
-void dis_ret ( VexMiscInfo* vmi, ULong d64 )
+void dis_ret ( VexAbiInfo* vbi, ULong d64 )
{
IRTemp t1 = newTemp(Ity_I64);
IRTemp t2 = newTemp(Ity_I64);
assign(t2, loadLE(Ity_I64,mkexpr(t1)));
assign(t3, binop(Iop_Add64, mkexpr(t1), mkU64(8+d64)));
putIReg64(R_RSP, mkexpr(t3));
- make_redzone_AbiHint(vmi, t3, "ret");
+ make_redzone_AbiHint(vbi, t3, "ret");
jmp_treg(Ijk_Ret,t2);
}
static void put_sse_roundingmode ( IRExpr* sseround )
{
- vassert(typeOfIRExpr(irbb->tyenv, sseround) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32);
stmt( IRStmt_Put( OFFB_SSEROUND,
unop(Iop_32Uto64,sseround) ) );
}
void* callback_opaque,
Long delta64,
VexArchInfo* archinfo,
- VexMiscInfo* vmi
+ VexAbiInfo* vmi
)
{
IRType ty;
stmt( IRStmt_Put(OFFB_TILEN, mkU64(lineszB) ) );
- irbb->jumpkind = Ijk_TInval;
- irbb->next = mkU64(guest_RIP_bbstart+delta);
+ irsb->jumpkind = Ijk_TInval;
+ irsb->next = mkU64(guest_RIP_bbstart+delta);
dres.whatNext = Dis_StopHere;
DIP("clflush %s\n", dis_buf);
/* Disassemble a single instruction into IR. The instruction
is located in host memory at &guest_code[delta]. */
-DisResult disInstr_AMD64 ( IRBB* irbb_IN,
+DisResult disInstr_AMD64 ( IRSB* irsb_IN,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian_IN )
{
DisResult dres;
/* Set globals (see top of this file) */
vassert(guest_arch == VexArchAMD64);
guest_code = guest_code_IN;
- irbb = irbb_IN;
+ irsb = irsb_IN;
host_is_bigendian = host_bigendian_IN;
guest_RIP_curr_instr = guest_IP;
guest_RIP_bbstart = guest_IP - delta;
guest_RIP_next_mustcheck = False;
dres = disInstr_AMD64_WRK ( put_IP, resteerOkFn, callback_opaque,
- delta, archinfo, miscinfo );
+ delta, archinfo, abiinfo );
/* If disInstr_AMD64_WRK tried to figure out the next rip, check it
got it right. Failure of this assertion is serious and denotes
/*---------------------------------------------------------*/
extern
-IRBB* bbToIR_ARM ( UChar* armCode,
+IRSB* bbToIR_ARM ( UChar* armCode,
Addr64 eip,
VexGuestExtents* vge,
Bool (*byte_accessible)(Addr64),
/* CONST */
static Addr32 guest_pc_bbstart;
-/* The IRBB* into which we're generating code. */
-static IRBB* irbb;
+/* The IRSB* into which we're generating code. */
+static IRSB* irsb;
/*------------------------------------------------------------*/
/* This is the main (only, in fact) entry point for this module. */
/* Disassemble a complete basic block, starting at guest_pc_start, and
- dumping the IR into global irbb. Returns the size, in bytes, of
+ dumping the IR into global irsb. Returns the size, in bytes, of
the basic block.
*/
-IRBB* bbToIR_ARM ( UChar* armCode,
+IRSB* bbToIR_ARM ( UChar* armCode,
Addr64 guest_pc_start,
VexGuestExtents* vge,
Bool (*byte_accessible)(Addr64),
host_is_bigendian = host_bigendian;
guest_code = armCode;
guest_pc_bbstart = (Addr32)guest_pc_start;
- irbb = emptyIRBB();
+ irsb = emptyIRSB();
vassert((guest_pc_start >> 32) == 0);
guest_next = 0;
resteerOK = toBool(n_instrs < vex_control.guest_chase_thresh);
- first_stmt_idx = irbb->stmts_used;
+ first_stmt_idx = irsb->stmts_used;
if (n_instrs > 0) {
/* for the first insn, the dispatch loop will have set
/* Print the resulting IR, if needed. */
if (vex_traceflags & VEX_TRACE_FE) {
- for (i = first_stmt_idx; i < irbb->stmts_used; i++) {
+ for (i = first_stmt_idx; i < irsb->stmts_used; i++) {
vex_printf(" ");
- ppIRStmt(irbb->stmts[i]);
+ ppIRStmt(irsb->stmts[i]);
vex_printf("\n");
}
}
if (dres == Dis_StopHere) {
- vassert(irbb->next != NULL);
+ vassert(irsb->next != NULL);
if (vex_traceflags & VEX_TRACE_FE) {
vex_printf(" ");
vex_printf( "goto {");
- ppIRJumpKind(irbb->jumpkind);
+ ppIRJumpKind(irsb->jumpkind);
vex_printf( "} ");
- ppIRExpr( irbb->next );
+ ppIRExpr( irsb->next );
vex_printf( "\n");
}
}
switch (dres) {
case Dis_Continue:
- vassert(irbb->next == NULL);
+ vassert(irsb->next == NULL);
if (n_instrs < vex_control.guest_max_insns) {
/* keep going */
} else {
- irbb->next = mkU32(toUInt(guest_pc_start+delta));
- return irbb;
+ irsb->next = mkU32(toUInt(guest_pc_start+delta));
+ return irsb;
}
break;
case Dis_StopHere:
- vassert(irbb->next != NULL);
- return irbb;
+ vassert(irsb->next != NULL);
+ return irsb;
case Dis_Resteer:
vpanic("bbToIR_ARM: Dis_Resteer: fixme");
/* need to add code here to start a new extent ... */
- vassert(irbb->next == NULL);
+ vassert(irsb->next == NULL);
/* figure out a new delta to continue at. */
vassert(chase_into_ok(guest_next));
delta = guest_next - guest_pc_start;
/*--- ARM insn stream. ---*/
/*------------------------------------------------------------*/
-/* Add a statement to the list held by "irbb". */
+/* Add a statement to the list held by "irsb". */
static void stmt ( IRStmt* st )
{
- addStmtToIRBB( irbb, st );
+ addStmtToIRSB( irsb, st );
}
/* Generate a new temporary of the given type. */
static IRTemp newTemp ( IRType ty )
{
vassert(isPlausibleIRType(ty));
- return newIRTemp( irbb->tyenv, ty );
+ return newIRTemp( irsb->tyenv, ty );
}
#if 0
static void assign ( IRTemp dst, IRExpr* e )
{
- stmt( IRStmt_Tmp(dst, e) );
+ stmt( IRStmt_WrTmp(dst, e) );
}
static void storeLE ( IRExpr* addr, IRExpr* data )
static IRExpr* mkexpr ( IRTemp tmp )
{
- return IRExpr_Tmp(tmp);
+ return IRExpr_RdTmp(tmp);
}
static IRExpr* mkU8 ( UChar i )
/* U-widen 8/16/32 bit int expr to 32. */
static IRExpr* widenUto32 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I32: return e;
case Ity_I16: return unop(Iop_16Uto32,e);
case Ity_I8: return unop(Iop_8Uto32,e);
/* S-widen 8/16/32 bit int expr to 32. */
static IRExpr* widenSto32 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I32: return e;
case Ity_I16: return unop(Iop_16Sto32,e);
case Ity_I8: return unop(Iop_8Sto32,e);
of these combinations make sense. */
static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e )
{
- IRType src_ty = typeOfIRExpr(irbb->tyenv,e);
+ IRType src_ty = typeOfIRExpr(irsb->tyenv,e);
if (src_ty == dst_ty)
return e;
if (src_ty == Ity_I32 && dst_ty == Ity_I16)
putIReg( Rd_addr, binop(Iop_And32, mkexpr(value), mkU32(0xFFFFFFFC)) );
// CAB: Need to tell vex we're doing a jump here?
- // irbb->jumpkind = Ijk_Boring;
- // irbb->next = mkexpr(value);
+ // irsb->jumpkind = Ijk_Boring;
+ // irsb->next = mkexpr(value);
} else {
putIReg( Rd_addr, mkexpr(value) );
}
branch_offset = extend_s_24to32( signed_immed_24 ) << 2;
assign( dest, binop(Iop_Add32, getIReg(15), mkU32(branch_offset)) );
- irbb->jumpkind = link ? Ijk_Call : Ijk_Boring;
- irbb->next = mkexpr(dest);
+ irsb->jumpkind = link ? Ijk_Call : Ijk_Boring;
+ irsb->next = mkexpr(dest);
// Note: Not actually writing to R15 - let the IR stuff do that.
*size = 24;
- irbb->next = mkU32(toUInt(guest_pc_bbstart+delta));
- irbb->jumpkind = Ijk_ClientReq;
+ irsb->next = mkU32(toUInt(guest_pc_bbstart+delta));
+ irsb->jumpkind = Ijk_ClientReq;
whatNext = Dis_StopHere;
goto decode_success;
stmt( IRStmt_Exit( mk_armg_calculate_condition(cond),
Ijk_Boring,
IRConst_U32(toUInt(guest_pc_bbstart+delta+4)) ) );
- //irbb->next = mkU32(guest_pc_bbstart+delta+4);
- //irbb->jumpkind = Ijk_Boring;
+ //irsb->next = mkU32(guest_pc_bbstart+delta+4);
+ //irsb->jumpkind = Ijk_Boring;
}
(In fact it's a VgInstrumentClosure.)
*/
-IRBB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
+IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
/*IN*/ void* callback_opaque,
/*IN*/ DisOneInstrFn dis_instr_fn,
/*IN*/ UChar* guest_code,
/*IN*/ Bool host_bigendian,
/*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
- /*IN*/ VexMiscInfo* miscinfo_both,
+ /*IN*/ VexAbiInfo* abiinfo_both,
/*IN*/ IRType guest_word_type,
/*IN*/ Bool do_self_check,
- /*IN*/ Bool (*preamble_function)(void*,IRBB*),
+ /*IN*/ Bool (*preamble_function)(void*,IRSB*),
/*IN*/ Int offB_TISTART,
/*IN*/ Int offB_TILEN )
{
static Int n_resteers = 0;
Int d_resteers = 0;
Int selfcheck_idx = 0;
- IRBB* irbb;
+ IRSB* irsb;
Addr64 guest_IP_curr_instr;
IRConst* guest_IP_bbstart_IRConst = NULL;
vge->base[0] = guest_IP_bbstart;
vge->len[0] = 0;
- /* And a new IR BB to dump the result into. */
- irbb = emptyIRBB();
+ /* And a new IR superblock to dump the result into. */
+ irsb = emptyIRSB();
/* Delta keeps track of how far along the guest_code array we have
so far gone. */
in which to put the check statements. We'll fill them in later
when we know the length and adler32 of the area to check. */
if (do_self_check) {
- selfcheck_idx = irbb->stmts_used;
- addStmtToIRBB( irbb, IRStmt_NoOp() );
- addStmtToIRBB( irbb, IRStmt_NoOp() );
- addStmtToIRBB( irbb, IRStmt_NoOp() );
- addStmtToIRBB( irbb, IRStmt_NoOp() );
- addStmtToIRBB( irbb, IRStmt_NoOp() );
+ selfcheck_idx = irsb->stmts_used;
+ addStmtToIRSB( irsb, IRStmt_NoOp() );
+ addStmtToIRSB( irsb, IRStmt_NoOp() );
+ addStmtToIRSB( irsb, IRStmt_NoOp() );
+ addStmtToIRSB( irsb, IRStmt_NoOp() );
+ addStmtToIRSB( irsb, IRStmt_NoOp() );
}
/* If the caller supplied a function to add its own preamble, use
it now. */
if (preamble_function) {
- Bool stopNow = preamble_function( callback_opaque, irbb );
+ Bool stopNow = preamble_function( callback_opaque, irsb );
if (stopNow) {
/* The callback has completed the IR block without any guest
insns being disassembled into it, so just return it at
this point, even if a self-check was requested - as there
is nothing to self-check. The five self-check no-ops will
still be in place, but they are harmless. */
- return irbb;
+ return irsb;
}
}
with. */
guest_IP_curr_instr = guest_IP_bbstart + delta;
- /* This is the irbb statement array index of the first stmt in
+ /* This is the irsb statement array index of the first stmt in
this insn. That will always be the instruction-mark
descriptor. */
- first_stmt_idx = irbb->stmts_used;
+ first_stmt_idx = irsb->stmts_used;
/* Add an instruction-mark statement. We won't know until after
disassembling the instruction how long it instruction is, so
just put in a zero length and we'll fix it up later. */
- addStmtToIRBB( irbb, IRStmt_IMark( guest_IP_curr_instr, 0 ));
+ addStmtToIRSB( irsb, IRStmt_IMark( guest_IP_curr_instr, 0 ));
/* for the first insn, the dispatch loop will have set
%IP, but for all the others we have to do it ourselves. */
need_to_put_IP = toBool(n_instrs > 0);
/* Finally, actually disassemble an instruction. */
- dres = dis_instr_fn ( irbb,
+ dres = dis_instr_fn ( irsb,
need_to_put_IP,
resteerOKfn,
callback_opaque,
guest_IP_curr_instr,
arch_guest,
archinfo_guest,
- miscinfo_both,
+ abiinfo_both,
host_bigendian );
/* stay sane ... */
vassert(dres.continueAt == 0);
/* Fill in the insn-mark length field. */
- vassert(first_stmt_idx >= 0 && first_stmt_idx < irbb->stmts_used);
- imark = irbb->stmts[first_stmt_idx];
+ vassert(first_stmt_idx >= 0 && first_stmt_idx < irsb->stmts_used);
+ imark = irsb->stmts[first_stmt_idx];
vassert(imark);
vassert(imark->tag == Ist_IMark);
vassert(imark->Ist.IMark.len == 0);
/* Print the resulting IR, if needed. */
if (vex_traceflags & VEX_TRACE_FE) {
- for (i = first_stmt_idx; i < irbb->stmts_used; i++) {
+ for (i = first_stmt_idx; i < irsb->stmts_used; i++) {
vex_printf(" ");
- ppIRStmt(irbb->stmts[i]);
+ ppIRStmt(irsb->stmts[i]);
vex_printf("\n");
}
}
/* If dis_instr_fn terminated the BB at this point, check it
- also filled in the irbb->next field. */
+ also filled in the irsb->next field. */
if (dres.whatNext == Dis_StopHere) {
- vassert(irbb->next != NULL);
+ vassert(irsb->next != NULL);
if (debug_print) {
vex_printf(" ");
vex_printf( "goto {");
- ppIRJumpKind(irbb->jumpkind);
+ ppIRJumpKind(irsb->jumpkind);
vex_printf( "} ");
- ppIRExpr( irbb->next );
+ ppIRExpr( irsb->next );
vex_printf( "\n");
}
}
switch (dres.whatNext) {
case Dis_Continue:
- vassert(irbb->next == NULL);
+ vassert(irsb->next == NULL);
if (n_instrs < vex_control.guest_max_insns) {
/* keep going */
} else {
/* We have to stop. */
- irbb->next
+ irsb->next
= IRExpr_Const(
guest_word_type == Ity_I32
? IRConst_U32(toUInt(guest_IP_bbstart+delta))
}
break;
case Dis_StopHere:
- vassert(irbb->next != NULL);
+ vassert(irsb->next != NULL);
goto done;
case Dis_Resteer:
/* Check that we actually allowed a resteer .. */
vassert(resteerOK);
- vassert(irbb->next == NULL);
+ vassert(irsb->next == NULL);
/* figure out a new delta to continue at. */
vassert(resteerOKfn(callback_opaque,dres.continueAt));
delta = dres.continueAt - guest_IP_bbstart;
the area of guest code to invalidate should we exit with a
self-check failure. */
- tistart_tmp = newIRTemp(irbb->tyenv, guest_word_type);
- tilen_tmp = newIRTemp(irbb->tyenv, guest_word_type);
+ tistart_tmp = newIRTemp(irsb->tyenv, guest_word_type);
+ tilen_tmp = newIRTemp(irsb->tyenv, guest_word_type);
- irbb->stmts[selfcheck_idx+0]
- = IRStmt_Tmp(tistart_tmp, IRExpr_Const(guest_IP_bbstart_IRConst) );
+ irsb->stmts[selfcheck_idx+0]
+ = IRStmt_WrTmp(tistart_tmp, IRExpr_Const(guest_IP_bbstart_IRConst) );
- irbb->stmts[selfcheck_idx+1]
- = IRStmt_Tmp(tilen_tmp,
- guest_word_type==Ity_I32
- ? IRExpr_Const(IRConst_U32(len2check))
- : IRExpr_Const(IRConst_U64(len2check))
+ irsb->stmts[selfcheck_idx+1]
+ = IRStmt_WrTmp(tilen_tmp,
+ guest_word_type==Ity_I32
+ ? IRExpr_Const(IRConst_U32(len2check))
+ : IRExpr_Const(IRConst_U64(len2check))
);
- irbb->stmts[selfcheck_idx+2]
- = IRStmt_Put( offB_TISTART, IRExpr_Tmp(tistart_tmp) );
+ irsb->stmts[selfcheck_idx+2]
+ = IRStmt_Put( offB_TISTART, IRExpr_RdTmp(tistart_tmp) );
- irbb->stmts[selfcheck_idx+3]
- = IRStmt_Put( offB_TILEN, IRExpr_Tmp(tilen_tmp) );
+ irsb->stmts[selfcheck_idx+3]
+ = IRStmt_Put( offB_TILEN, IRExpr_RdTmp(tilen_tmp) );
- p_adler_helper = miscinfo_both->host_ppc_calls_use_fndescrs
+ p_adler_helper = abiinfo_both->host_ppc_calls_use_fndescrs
? ((HWord*)(&genericg_compute_adler32))[0]
: (HWord)&genericg_compute_adler32;
- irbb->stmts[selfcheck_idx+4]
+ irsb->stmts[selfcheck_idx+4]
= IRStmt_Exit(
IRExpr_Binop(
Iop_CmpNE32,
);
}
- return irbb;
+ return irsb;
}
DisResult (*DisOneInstrFn) (
- /* This is the IRBB to which the resulting IR is to be appended. */
- /*OUT*/ IRBB* irbb,
+ /* This is the IRSB to which the resulting IR is to be appended. */
+ /*OUT*/ IRSB* irbb,
/* Do we need to generate IR to set the guest IP for this insn,
or not? */
/*IN*/ VexArch guest_arch,
/*IN*/ VexArchInfo* archinfo,
- /* Misc info about guest and host */
- /*IN*/ VexMiscInfo* miscinfo,
+ /* ABI info for both guest and host */
+ /*IN*/ VexAbiInfo* abiinfo,
/* Is the host bigendian? */
/*IN*/ Bool host_bigendian
/* See detailed comment in bb_to_IR.c. */
extern
-IRBB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
+IRSB* bb_to_IR ( /*OUT*/VexGuestExtents* vge,
/*IN*/ void* closure_opaque,
/*IN*/ DisOneInstrFn dis_instr_fn,
/*IN*/ UChar* guest_code,
/*IN*/ Bool host_bigendian,
/*IN*/ VexArch arch_guest,
/*IN*/ VexArchInfo* archinfo_guest,
- /*IN*/ VexMiscInfo* miscinfo_both,
+ /*IN*/ VexAbiInfo* abiinfo_both,
/*IN*/ IRType guest_word_type,
/*IN*/ Bool do_self_check,
- /*IN*/ Bool (*preamble_function)(void*,IRBB*),
+ /*IN*/ Bool (*preamble_function)(void*,IRSB*),
/*IN*/ Int offB_TISTART,
/*IN*/ Int offB_TILEN );
/* Convert one ppc insn to IR. See the type DisOneInstrFn in
bb_to_IR.h. */
extern
-DisResult disInstr_PPC ( IRBB* irbb,
+DisResult disInstr_PPC ( IRSB* irbb,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian );
/* Used by the optimiser to specialise calls to helpers. */
translated. */
static Addr64 guest_CIA_curr_instr;
-/* The IRBB* into which we're generating code. */
-static IRBB* irbb;
+/* The IRSB* into which we're generating code. */
+static IRSB* irsb;
/* Is our guest binary 32 or 64bit? Set at each call to
disInstr_PPC below. */
// most platforms it's the identity function. Unfortunately, on
// ppc64-linux it isn't (sigh) and ditto for ppc32-aix5 and
// ppc64-aix5.
-static void* fnptr_to_fnentry( VexMiscInfo* vmi, void* f )
+static void* fnptr_to_fnentry( VexAbiInfo* vbi, void* f )
{
- if (vmi->host_ppc_calls_use_fndescrs) {
+ if (vbi->host_ppc_calls_use_fndescrs) {
/* f is a pointer to a 3-word function descriptor, of which the
first word is the entry address. */
/* note, this is correct even with cross-jitting, since this is
/*--- ppc32/64 insn stream. ---*/
/*------------------------------------------------------------*/
-/* Add a statement to the list held by "irbb". */
+/* Add a statement to the list held by "irsb". */
static void stmt ( IRStmt* st )
{
- addStmtToIRBB( irbb, st );
+ addStmtToIRSB( irsb, st );
}
/* Generate a new temporary of the given type. */
static IRTemp newTemp ( IRType ty )
{
vassert(isPlausibleIRType(ty));
- return newIRTemp( irbb->tyenv, ty );
+ return newIRTemp( irsb->tyenv, ty );
}
/* Various simple conversions */
static void assign ( IRTemp dst, IRExpr* e )
{
- stmt( IRStmt_Tmp(dst, e) );
+ stmt( IRStmt_WrTmp(dst, e) );
}
static void storeBE ( IRExpr* addr, IRExpr* data )
{
- vassert(typeOfIRExpr(irbb->tyenv, addr) == Ity_I32 ||
- typeOfIRExpr(irbb->tyenv, addr) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, addr) == Ity_I32 ||
+ typeOfIRExpr(irsb->tyenv, addr) == Ity_I64);
stmt( IRStmt_Store(Iend_BE,addr,data) );
}
static IRExpr* mkexpr ( IRTemp tmp )
{
- return IRExpr_Tmp(tmp);
+ return IRExpr_RdTmp(tmp);
}
static IRExpr* mkU8 ( UChar i )
static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 )
{
- vassert(typeOfIRExpr(irbb->tyenv, arg1) == Ity_I1);
- vassert(typeOfIRExpr(irbb->tyenv, arg2) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1);
return unop(Iop_32to1, binop(Iop_Or32, unop(Iop_1Uto32, arg1),
unop(Iop_1Uto32, arg2)));
}
static IRExpr* mkAND1 ( IRExpr* arg1, IRExpr* arg2 )
{
- vassert(typeOfIRExpr(irbb->tyenv, arg1) == Ity_I1);
- vassert(typeOfIRExpr(irbb->tyenv, arg2) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv, arg1) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv, arg2) == Ity_I1);
return unop(Iop_32to1, binop(Iop_And32, unop(Iop_1Uto32, arg1),
unop(Iop_1Uto32, arg2)));
}
{
IRTemp ones8x16 = newTemp(Ity_V128);
- vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128);
vassert(vEvn && *vEvn == IRTemp_INVALID);
vassert(vOdd && *vOdd == IRTemp_INVALID);
*vEvn = newTemp(Ity_V128);
{
IRTemp ones8x16 = newTemp(Ity_V128);
- vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128);
vassert(vEvn && *vEvn == IRTemp_INVALID);
vassert(vOdd && *vOdd == IRTemp_INVALID);
*vEvn = newTemp(Ity_V128);
{
IRTemp ones16x8 = newTemp(Ity_V128);
- vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128);
vassert(vEvn && *vEvn == IRTemp_INVALID);
vassert(vOdd && *vOdd == IRTemp_INVALID);
*vEvn = newTemp(Ity_V128);
{
IRTemp ones16x8 = newTemp(Ity_V128);
- vassert(typeOfIRExpr(irbb->tyenv, vIn) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, vIn) == Ity_V128);
vassert(vEvn && *vEvn == IRTemp_INVALID);
vassert(vOdd && *vOdd == IRTemp_INVALID);
*vEvn = newTemp(Ity_V128);
IRTemp hi64 = newTemp(Ity_I64);
IRTemp lo64 = newTemp(Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t128) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128);
vassert(t0 && *t0 == IRTemp_INVALID);
vassert(t1 && *t1 == IRTemp_INVALID);
vassert(t2 && *t2 == IRTemp_INVALID);
IRTemp hi64 = newTemp(Ity_I64);
IRTemp lo64 = newTemp(Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t128) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, t128) == Ity_V128);
vassert(t0 && *t0 == IRTemp_INVALID);
vassert(t1 && *t1 == IRTemp_INVALID);
vassert(t2 && *t2 == IRTemp_INVALID);
IRTemp hi32 = newTemp(Ity_I32);
IRTemp lo32 = newTemp(Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv, t64) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t64) == Ity_I64);
assign( hi32, unop(Iop_64HIto32, t64));
assign( lo32, unop(Iop_64to32, t64));
IRTemp hi32 = newTemp(Ity_I32);
IRTemp lo32 = newTemp(Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv, t64) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t64) == Ity_I64);
assign( hi32, unop(Iop_64HIto32, t64));
assign( lo32, unop(Iop_64to32, t64));
static IRExpr* mkV128from4x64S ( IRExpr* t3, IRExpr* t2,
IRExpr* t1, IRExpr* t0 )
{
- vassert(typeOfIRExpr(irbb->tyenv, t3) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t2) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t1) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t0) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t3) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t2) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t1) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t0) == Ity_I64);
return binop(Iop_64HLtoV128,
binop(Iop_32HLto64,
mkQNarrow64Sto32( t3 ),
static IRExpr* mkV128from4x64U ( IRExpr* t3, IRExpr* t2,
IRExpr* t1, IRExpr* t0 )
{
- vassert(typeOfIRExpr(irbb->tyenv, t3) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t2) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t1) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv, t0) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t3) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t2) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t1) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, t0) == Ity_I64);
return binop(Iop_64HLtoV128,
binop(Iop_32HLto64,
mkQNarrow64Uto32( t3 ),
static IRExpr* /* :: Ity_I64 */ mk64lo32Sto64 ( IRExpr* src )
{
- vassert(typeOfIRExpr(irbb->tyenv, src) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, src) == Ity_I64);
return unop(Iop_32Sto64, unop(Iop_64to32, src));
}
static IRExpr* /* :: Ity_I64 */ mk64lo32Uto64 ( IRExpr* src )
{
- vassert(typeOfIRExpr(irbb->tyenv, src) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv, src) == Ity_I64);
return unop(Iop_32Uto64, unop(Iop_64to32, src));
}
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
vassert(archreg < 32);
- vassert(typeOfIRExpr(irbb->tyenv, e) == ty );
+ vassert(typeOfIRExpr(irsb->tyenv, e) == ty );
stmt( IRStmt_Put(integerGuestRegOffset(archreg), e) );
}
static void putFReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 32);
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_F64);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
stmt( IRStmt_Put(floatGuestRegOffset(archreg), e) );
}
static void putVReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 32);
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_V128);
stmt( IRStmt_Put(vectorGuestRegOffset(archreg), e) );
}
IRExpr* rot_amt )
{
IRExpr *mask, *rot;
- vassert(typeOfIRExpr(irbb->tyenv,rot_amt) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv,rot_amt) == Ity_I8);
- if (typeOfIRExpr(irbb->tyenv,src) == Ity_I64) {
+ if (typeOfIRExpr(irsb->tyenv,src) == Ity_I64) {
// rot = (src << rot_amt) | (src >> (64-rot_amt))
mask = binop(Iop_And8, rot_amt, mkU8(63));
rot = binop(Iop_Or64,
{
IRExpr *mask, *rot32;
vassert(mode64); // used only in 64bit mode
- vassert(typeOfIRExpr(irbb->tyenv,src64) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,rot_amt) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv,src64) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,rot_amt) == Ity_I8);
mask = binop(Iop_And8, rot_amt, mkU8(31));
rot32 = ROTL( unop(Iop_64to32, src64), rot_amt );
vpanic("addr_align(ppc)");
}
- vassert(typeOfIRExpr(irbb->tyenv,addr) == ty);
+ vassert(typeOfIRExpr(irsb->tyenv,addr) == ty);
return binop( mkSzOp(ty, Iop_And8), addr, mkSzImm(ty, mask) );
}
N) becomes undefined. That is at function calls and returns. ELF
ppc32 doesn't have this "feature" (how fortunate for it).
*/
-static void make_redzone_AbiHint ( VexMiscInfo* vmi, HChar* who )
+static void make_redzone_AbiHint ( VexAbiInfo* vbi, HChar* who )
{
- Int szB = vmi->guest_stack_redzone_size;
+ Int szB = vbi->guest_stack_redzone_size;
if (0) vex_printf("AbiHint: %s\n", who);
vassert(szB >= 0);
if (szB > 0) {
static void putCR321 ( UInt cr, IRExpr* e )
{
vassert(cr < 8);
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
stmt( IRStmt_Put(guestCR321offset(cr), e) );
}
static void putCR0 ( UInt cr, IRExpr* e )
{
vassert(cr < 8);
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
stmt( IRStmt_Put(guestCR0offset(cr), e) );
}
{
UInt n, off;
IRExpr* safe;
- vassert(typeOfIRExpr(irbb->tyenv,bit) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,bit) == Ity_I32);
safe = binop(Iop_And32, bit, mkU32(1));
n = bi / 4;
off = bi % 4;
static IRExpr* getXER_SO ( void );
static void set_CR0 ( IRExpr* result )
{
- vassert(typeOfIRExpr(irbb->tyenv,result) == Ity_I32 ||
- typeOfIRExpr(irbb->tyenv,result) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_I32 ||
+ typeOfIRExpr(irsb->tyenv,result) == Ity_I64);
if (mode64) {
putCR321( 0, unop(Iop_64to8,
binop(Iop_CmpORD64S, result, mkU64(0))) );
IRTemp rOnes = newTemp(Ity_I8);
IRTemp rZeros = newTemp(Ity_I8);
- vassert(typeOfIRExpr(irbb->tyenv,result) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv,result) == Ity_V128);
assign( v0, result );
assign( v1, binop(Iop_ShrV128, result, mkU8(32)) );
static void putXER_SO ( IRExpr* e )
{
IRExpr* so;
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
so = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_SO, so ) );
}
static void putXER_OV ( IRExpr* e )
{
IRExpr* ov;
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ov = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_OV, ov ) );
}
static void putXER_CA ( IRExpr* e )
{
IRExpr* ca;
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
ca = binop(Iop_And8, e, mkU8(1));
stmt( IRStmt_Put( OFFB_XER_CA, ca ) );
}
static void putXER_BC ( IRExpr* e )
{
IRExpr* bc;
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I8);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I8);
bc = binop(Iop_And8, e, mkU8(0x7F));
stmt( IRStmt_Put( OFFB_XER_BC, bc ) );
}
IRTemp t64;
IRExpr* xer_ov;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
# define INT32_MIN 0x80000000
{
IRExpr* xer_ov;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
# define INT64_MIN 0x8000000000000000ULL
{
IRExpr* xer_ca;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I32);
- vassert(typeOfIRExpr(irbb->tyenv,oldca) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I32);
/* Incoming oldca is assumed to hold the values 0 or 1 only. This
seems reasonable given that it's always generated by
{
IRExpr* xer_ca;
vassert(op < PPCG_FLAG_OP_NUMBER);
- vassert(typeOfIRExpr(irbb->tyenv,res) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,argL) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,argR) == Ity_I64);
- vassert(typeOfIRExpr(irbb->tyenv,oldca) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,res) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argL) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,argR) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,oldca) == Ity_I64);
/* Incoming oldca is assumed to hold the values 0 or 1 only. This
seems reasonable given that it's always generated by
static void putGST ( PPC_GST reg, IRExpr* src )
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
- IRType ty_src = typeOfIRExpr(irbb->tyenv,src );
+ IRType ty_src = typeOfIRExpr(irsb->tyenv,src );
vassert( reg < PPC_GST_MAX );
switch (reg) {
case PPC_GST_CIA_AT_SC:
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
vassert( reg < PPC_GST_MAX );
- vassert( typeOfIRExpr(irbb->tyenv,src ) == Ity_I32 );
+ vassert( typeOfIRExpr(irsb->tyenv,src ) == Ity_I32 );
switch (reg) {
case PPC_GST_FPSCR: {
{
UInt shft, mask;
- vassert( typeOfIRExpr(irbb->tyenv,src ) == Ity_I32 );
+ vassert( typeOfIRExpr(irsb->tyenv,src ) == Ity_I32 );
vassert( fld < 8 );
vassert( reg < PPC_GST_MAX );
remove the false dependency, which has been known to cause
memcheck to produce false errors. */
if (rA_addr == rB_addr)
- a = b = typeOfIRExpr(irbb->tyenv,a) == Ity_I64
+ a = b = typeOfIRExpr(irsb->tyenv,a) == Ity_I64
? mkU64(0) : mkU32(0);
if (flag_L == 1) {
putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64S, a, b)));
remove the false dependency, which has been known to cause
memcheck to produce false errors. */
if (rA_addr == rB_addr)
- a = b = typeOfIRExpr(irbb->tyenv,a) == Ity_I64
+ a = b = typeOfIRExpr(irsb->tyenv,a) == Ity_I64
? mkU64(0) : mkU32(0);
if (flag_L == 1) {
putCR321(crfD, unop(Iop_64to8, binop(Iop_CmpORD64U, a, b)));
/*
Integer Store Instructions
*/
-static Bool dis_int_store ( UInt theInstr, VexMiscInfo* vmi )
+static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
{
/* D-Form, X-Form, DS-Form */
UChar opc1 = ifieldOPC(theInstr);
Integer Branch Instructions
*/
static Bool dis_branch ( UInt theInstr,
- VexMiscInfo* vmi,
+ VexAbiInfo* vbi,
/*OUT*/DisResult* dres,
Bool (*resteerOkFn)(void*,Addr64),
void* callback_opaque )
if (flag_LK) {
putGST( PPC_GST_LR, e_nia );
- if (vmi->guest_ppc_zap_RZ_at_bl
- && vmi->guest_ppc_zap_RZ_at_bl( (ULong)tgt) )
- make_redzone_AbiHint( vmi,
+ if (vbi->guest_ppc_zap_RZ_at_bl
+ && vbi->guest_ppc_zap_RZ_at_bl( (ULong)tgt) )
+ make_redzone_AbiHint( vbi,
"branch-and-link (unconditional call)" );
}
dres->whatNext = Dis_Resteer;
dres->continueAt = tgt;
} else {
- irbb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
- irbb->next = mkSzImm(ty, tgt);
+ irsb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
+ irsb->next = mkSzImm(ty, tgt);
}
break;
flag_LK ? Ijk_Call : Ijk_Boring,
mkSzConst(ty, tgt) ) );
- irbb->jumpkind = Ijk_Boring;
- irbb->next = e_nia;
+ irsb->jumpkind = Ijk_Boring;
+ irsb->next = e_nia;
break;
case 0x13:
Ijk_Boring,
c_nia ));
- irbb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
- irbb->next = mkexpr(lr_old);
+ irsb->jumpkind = flag_LK ? Ijk_Call : Ijk_Boring;
+ irsb->next = mkexpr(lr_old);
break;
case 0x010: { // bclr (Branch Cond. to Link Register, PPC32 p365)
Ijk_Boring,
c_nia ));
- if (vanilla_return && vmi->guest_ppc_zap_RZ_at_blr)
- make_redzone_AbiHint( vmi, "branch-to-lr (unconditional return)" );
+ if (vanilla_return && vbi->guest_ppc_zap_RZ_at_blr)
+ make_redzone_AbiHint( vbi, "branch-to-lr (unconditional return)" );
/* blrl is pretty strange; it's like a return that sets the
return address of its caller to the insn following this
one. Mark it as a return. */
- irbb->jumpkind = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */
- irbb->next = mkexpr(lr_old);
+ irsb->jumpkind = Ijk_Ret; /* was flag_LK ? Ijk_Call : Ijk_Ret; */
+ irsb->next = mkexpr(lr_old);
break;
}
default:
if (uncond) {
/* If the trap shows signs of being unconditional, don't
continue decoding past it. */
- irbb->next = mkSzImm( ty, nextInsnAddr() );
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkSzImm( ty, nextInsnAddr() );
+ irsb->jumpkind = Ijk_Boring;
dres->whatNext = Dis_StopHere;
}
System Linkage Instructions
*/
static Bool dis_syslink ( UInt theInstr,
- VexMiscInfo* miscinfo, DisResult* dres )
+ VexAbiInfo* abiinfo, DisResult* dres )
{
IRType ty = mode64 ? Ity_I64 : Ity_I32;
/* It's important that all ArchRegs carry their up-to-date value
at this point. So we declare an end-of-block here, which
forces any TempRegs caching ArchRegs to be flushed. */
- /* At this point, AIX's behaviour differs from Linux's: AIX resumes
- after the syscall at %lr, whereas Linux does the obvious thing
- and resumes at the next instruction. Hence we need to encode
- that into the generated IR. */
- irbb->next = miscinfo->guest_ppc_sc_continues_at_LR
- ? /*AIXishly*/getGST( PPC_GST_LR )
- : /*Linuxfully*/mkSzImm( ty, nextInsnAddr() );
- irbb->jumpkind = Ijk_Sys_syscall;
+ irsb->next = abiinfo->guest_ppc_sc_continues_at_LR
+ ? getGST( PPC_GST_LR )
+ : mkSzImm( ty, nextInsnAddr() );
+ irsb->jumpkind = Ijk_Sys_syscall;
dres->whatNext = Dis_StopHere;
return True;
/* Generates code to swap the byte order in an Ity_I32. */
static IRExpr* /* :: Ity_I32 */ gen_byterev32 ( IRTemp t )
{
- vassert(typeOfIRTemp(irbb->tyenv, t) == Ity_I32);
+ vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32);
return
binop(Iop_Or32,
binop(Iop_Shl32, mkexpr(t), mkU8(24)),
and zeroes the upper half. */
static IRExpr* /* :: Ity_I32 */ gen_byterev16 ( IRTemp t )
{
- vassert(typeOfIRTemp(irbb->tyenv, t) == Ity_I32);
+ vassert(typeOfIRTemp(irsb->tyenv, t) == Ity_I32);
return
binop(Iop_Or32,
binop(Iop_And32, binop(Iop_Shl32, mkexpr(t), mkU8(8)),
/*
Processor Control Instructions
*/
-static Bool dis_proc_ctl ( VexMiscInfo* vmi, UInt theInstr )
+static Bool dis_proc_ctl ( VexAbiInfo* vbi, UInt theInstr )
{
UChar opc1 = ifieldOPC(theInstr);
val,
0/*regparms*/,
"ppcg_dirtyhelper_MFTB",
- fnptr_to_fnentry(vmi, &ppcg_dirtyhelper_MFTB),
+ fnptr_to_fnentry(vbi, &ppcg_dirtyhelper_MFTB),
args );
/* execute the dirty call, dumping the result in val. */
stmt( IRStmt_Dirty(d) );
/* be paranoid ... */
stmt( IRStmt_MFence() );
- irbb->jumpkind = Ijk_TInval;
- irbb->next = mkSzImm(ty, nextInsnAddr());
+ irsb->jumpkind = Ijk_TInval;
+ irsb->next = mkSzImm(ty, nextInsnAddr());
dres->whatNext = Dis_StopHere;
break;
}
/*
AltiVec Load Instructions
*/
-static Bool dis_av_load ( VexMiscInfo* vmi, UInt theInstr )
+static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
{
/* X-Form */
UChar opc1 = ifieldOPC(theInstr);
d = unsafeIRDirty_0_N (
0/*regparms*/,
"ppc32g_dirtyhelper_LVS",
- fnptr_to_fnentry(vmi, &ppc32g_dirtyhelper_LVS),
+ fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS),
args );
} else {
d = unsafeIRDirty_0_N (
0/*regparms*/,
"ppc64g_dirtyhelper_LVS",
- fnptr_to_fnentry(vmi, &ppc64g_dirtyhelper_LVS),
+ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
args );
}
DIP("lvsl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
d = unsafeIRDirty_0_N (
0/*regparms*/,
"ppc32g_dirtyhelper_LVS",
- fnptr_to_fnentry(vmi, &ppc32g_dirtyhelper_LVS),
+ fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS),
args );
} else {
d = unsafeIRDirty_0_N (
0/*regparms*/,
"ppc64g_dirtyhelper_LVS",
- fnptr_to_fnentry(vmi, &ppc64g_dirtyhelper_LVS),
+ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
args );
}
DIP("lvsr v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
void* callback_opaque,
Long delta64,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo
+ VexAbiInfo* abiinfo
)
{
UChar opc1;
/* %R3 = client_request ( %R4 ) */
DIP("r3 = client_request ( %%r4 )\n");
delta += 20;
- irbb->next = mkSzImm( ty, guest_CIA_bbstart + delta );
- irbb->jumpkind = Ijk_ClientReq;
+ irsb->next = mkSzImm( ty, guest_CIA_bbstart + delta );
+ irsb->jumpkind = Ijk_ClientReq;
dres.whatNext = Dis_StopHere;
goto decode_success;
}
DIP("branch-and-link-to-noredir r11\n");
delta += 20;
putGST( PPC_GST_LR, mkSzImm(ty, guest_CIA_bbstart + (Long)delta) );
- irbb->next = getIReg(11);
- irbb->jumpkind = Ijk_NoRedir;
+ irsb->next = getIReg(11);
+ irsb->jumpkind = Ijk_NoRedir;
dres.whatNext = Dis_StopHere;
goto decode_success;
}
/* Integer Store Instructions */
case 0x26: case 0x27: case 0x2C: // stb, stbu, sth
case 0x2D: case 0x24: case 0x25: // sthu, stw, stwu
- if (dis_int_store( theInstr, miscinfo )) goto decode_success;
+ if (dis_int_store( theInstr, abiinfo )) goto decode_success;
goto decode_failure;
/* Integer Load and Store Multiple Instructions */
/* Branch Instructions */
case 0x12: case 0x10: // b, bc
- if (dis_branch(theInstr, miscinfo, &dres,
+ if (dis_branch(theInstr, abiinfo, &dres,
resteerOkFn, callback_opaque))
goto decode_success;
goto decode_failure;
/* System Linkage Instructions */
case 0x11: // sc
- if (dis_syslink(theInstr, miscinfo, &dres)) goto decode_success;
+ if (dis_syslink(theInstr, abiinfo, &dres)) goto decode_success;
goto decode_failure;
/* Trap Instructions */
/* 64bit Integer Stores */
case 0x3E: // std, stdu
if (!mode64) goto decode_failure;
- if (dis_int_store( theInstr, miscinfo )) goto decode_success;
+ if (dis_int_store( theInstr, abiinfo )) goto decode_success;
goto decode_failure;
case 0x3F:
/* Branch Instructions */
case 0x210: case 0x010: // bcctr, bclr
- if (dis_branch(theInstr, miscinfo, &dres,
+ if (dis_branch(theInstr, abiinfo, &dres,
resteerOkFn, callback_opaque))
goto decode_success;
goto decode_failure;
/* Integer Store Instructions */
case 0x0F7: case 0x0D7: case 0x1B7: // stbux, stbx, sthux
case 0x197: case 0x0B7: case 0x097: // sthx, stwux, stwx
- if (dis_int_store( theInstr, miscinfo )) goto decode_success;
+ if (dis_int_store( theInstr, abiinfo )) goto decode_success;
goto decode_failure;
/* 64bit Integer Store Instructions */
case 0x0B5: case 0x095: // stdux, stdx
if (!mode64) goto decode_failure;
- if (dis_int_store( theInstr, miscinfo )) goto decode_success;
+ if (dis_int_store( theInstr, abiinfo )) goto decode_success;
goto decode_failure;
/* Integer Load and Store with Byte Reverse Instructions */
Bool ok = dis_int_ldst_str( theInstr, &stopHere );
if (!ok) goto decode_failure;
if (stopHere) {
- irbb->next = mkSzImm(ty, nextInsnAddr());
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkSzImm(ty, nextInsnAddr());
+ irsb->jumpkind = Ijk_Boring;
dres.whatNext = Dis_StopHere;
}
goto decode_success;
/* Processor Control Instructions */
case 0x200: case 0x013: case 0x153: // mcrxr, mfcr, mfspr
case 0x173: case 0x090: case 0x1D3: // mftb, mtcrf, mtspr
- if (dis_proc_ctl( miscinfo, theInstr )) goto decode_success;
+ if (dis_proc_ctl( abiinfo, theInstr )) goto decode_success;
goto decode_failure;
/* Cache Management Instructions */
case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx
case 0x067: case 0x167: // lvx, lvxl
if (!allow_V) goto decode_noV;
- if (dis_av_load( miscinfo, theInstr )) goto decode_success;
+ if (dis_av_load( abiinfo, theInstr )) goto decode_success;
goto decode_failure;
/* AV Store */
insn, but nevertheless be paranoid and update it again right
now. */
putGST( PPC_GST_CIA, mkSzImm(ty, guest_CIA_curr_instr) );
- irbb->next = mkSzImm(ty, guest_CIA_curr_instr);
- irbb->jumpkind = Ijk_NoDecode;
+ irsb->next = mkSzImm(ty, guest_CIA_curr_instr);
+ irsb->jumpkind = Ijk_NoDecode;
dres.whatNext = Dis_StopHere;
dres.len = 0;
return dres;
/* Disassemble a single instruction into IR. The instruction
is located in host memory at &guest_code[delta]. */
-DisResult disInstr_PPC ( IRBB* irbb_IN,
+DisResult disInstr_PPC ( IRSB* irsb_IN,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian_IN )
{
IRType ty;
/* Set globals (see top of this file) */
guest_code = guest_code_IN;
- irbb = irbb_IN;
+ irsb = irsb_IN;
host_is_bigendian = host_bigendian_IN;
guest_CIA_curr_instr = mkSzAddr(ty, guest_IP);
guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta);
dres = disInstr_PPC_WRK ( put_IP, resteerOkFn, callback_opaque,
- delta, archinfo, miscinfo );
+ delta, archinfo, abiinfo );
return dres;
}
/* Convert one x86 insn to IR. See the type DisOneInstrFn in
bb_to_IR.h. */
extern
-DisResult disInstr_X86 ( IRBB* irbb,
+DisResult disInstr_X86 ( IRSB* irbb,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian );
/* Used by the optimiser to specialise calls to helpers. */
translated. */
static Addr32 guest_EIP_curr_instr;
-/* The IRBB* into which we're generating code. */
-static IRBB* irbb;
+/* The IRSB* into which we're generating code. */
+static IRSB* irsb;
/*------------------------------------------------------------*/
/* Add a statement to the list held by "irbb". */
static void stmt ( IRStmt* st )
{
- addStmtToIRBB( irbb, st );
+ addStmtToIRSB( irsb, st );
}
/* Generate a new temporary of the given type. */
static IRTemp newTemp ( IRType ty )
{
vassert(isPlausibleIRType(ty));
- return newIRTemp( irbb->tyenv, ty );
+ return newIRTemp( irsb->tyenv, ty );
}
/* Bomb out if we can't handle something. */
/* Ditto, but write to a reg instead. */
static void putIReg ( Int sz, UInt archreg, IRExpr* e )
{
- IRType ty = typeOfIRExpr(irbb->tyenv, e);
+ IRType ty = typeOfIRExpr(irsb->tyenv, e);
switch (sz) {
case 1: vassert(ty == Ity_I8); break;
case 2: vassert(ty == Ity_I16); break;
static void putSReg ( UInt sreg, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I16);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
stmt( IRStmt_Put( segmentGuestRegOffset(sreg), e ) );
}
static void putXMMReg ( UInt xmmreg, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_V128);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_V128);
stmt( IRStmt_Put( xmmGuestRegOffset(xmmreg), e ) );
}
static void putXMMRegLane64 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane64F ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_F64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F64);
stmt( IRStmt_Put( xmmGuestRegLane64offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane32F ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_F32);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_F32);
stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane32 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I32);
stmt( IRStmt_Put( xmmGuestRegLane32offset(xmmreg,laneno), e ) );
}
static void putXMMRegLane16 ( UInt xmmreg, Int laneno, IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I16);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I16);
stmt( IRStmt_Put( xmmGuestRegLane16offset(xmmreg,laneno), e ) );
}
static void assign ( IRTemp dst, IRExpr* e )
{
- stmt( IRStmt_Tmp(dst, e) );
+ stmt( IRStmt_WrTmp(dst, e) );
}
static void storeLE ( IRExpr* addr, IRExpr* data )
static IRExpr* mkexpr ( IRTemp tmp )
{
- return IRExpr_Tmp(tmp);
+ return IRExpr_RdTmp(tmp);
}
static IRExpr* mkU8 ( UInt i )
static IRExpr* mkAnd1 ( IRExpr* x, IRExpr* y )
{
- vassert(typeOfIRExpr(irbb->tyenv,x) == Ity_I1);
- vassert(typeOfIRExpr(irbb->tyenv,y) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv,x) == Ity_I1);
+ vassert(typeOfIRExpr(irsb->tyenv,y) == Ity_I1);
return unop(Iop_32to1,
binop(Iop_And32,
unop(Iop_1Uto32,x),
/* U-widen 8/16/32 bit int expr to 32. */
static IRExpr* widenUto32 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I32: return e;
case Ity_I16: return unop(Iop_16Uto32,e);
case Ity_I8: return unop(Iop_8Uto32,e);
/* S-widen 8/16/32 bit int expr to 32. */
static IRExpr* widenSto32 ( IRExpr* e )
{
- switch (typeOfIRExpr(irbb->tyenv,e)) {
+ switch (typeOfIRExpr(irsb->tyenv,e)) {
case Ity_I32: return e;
case Ity_I16: return unop(Iop_16Sto32,e);
case Ity_I8: return unop(Iop_8Sto32,e);
of these combinations make sense. */
static IRExpr* narrowTo ( IRType dst_ty, IRExpr* e )
{
- IRType src_ty = typeOfIRExpr(irbb->tyenv,e);
+ IRType src_ty = typeOfIRExpr(irsb->tyenv,e);
if (src_ty == dst_ty)
return e;
if (src_ty == Ity_I32 && dst_ty == Ity_I16)
static void jmp_lit( IRJumpKind kind, Addr32 d32 )
{
- irbb->next = mkU32(d32);
- irbb->jumpkind = kind;
+ irsb->next = mkU32(d32);
+ irsb->jumpkind = kind;
}
static void jmp_treg( IRJumpKind kind, IRTemp t )
{
- irbb->next = mkexpr(t);
- irbb->jumpkind = kind;
+ irsb->next = mkexpr(t);
+ irsb->jumpkind = kind;
}
static
stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos),
Ijk_Boring,
IRConst_U32(d32_false) ) );
- irbb->next = mkU32(d32_true);
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkU32(d32_true);
+ irsb->jumpkind = Ijk_Boring;
} else {
stmt( IRStmt_Exit( mk_x86g_calculate_condition(condPos),
Ijk_Boring,
IRConst_U32(d32_true) ) );
- irbb->next = mkU32(d32_false);
- irbb->jumpkind = Ijk_Boring;
+ irsb->next = mkU32(d32_false);
+ irsb->jumpkind = Ijk_Boring;
}
}
static void put_emwarn ( IRExpr* e /* :: Ity_I32 */ )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
stmt( IRStmt_Put( OFFB_EMWARN, e ) );
}
static void put_ftop ( IRExpr* e )
{
- vassert(typeOfIRExpr(irbb->tyenv, e) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_I32);
stmt( IRStmt_Put( OFFB_FTOP, e ) );
}
static void put_ST_TAG ( Int i, IRExpr* value )
{
- IRArray* descr;
- vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_I8);
- descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRRegArray* descr;
+ vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_I8);
+ descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
}
static IRExpr* get_ST_TAG ( Int i )
{
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
return IRExpr_GetI( descr, get_ftop(), i );
}
static void put_ST_UNCHECKED ( Int i, IRExpr* value )
{
- IRArray* descr;
- vassert(typeOfIRExpr(irbb->tyenv, value) == Ity_F64);
- descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
+ IRRegArray* descr;
+ vassert(typeOfIRExpr(irsb->tyenv, value) == Ity_F64);
+ descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
stmt( IRStmt_PutI( descr, get_ftop(), i, value ) );
/* Mark the register as in-use. */
put_ST_TAG(i, mkU8(1));
static IRExpr* get_ST_UNCHECKED ( Int i )
{
- IRArray* descr = mkIRArray( OFFB_FPREGS, Ity_F64, 8 );
+ IRRegArray* descr = mkIRRegArray( OFFB_FPREGS, Ity_F64, 8 );
return IRExpr_GetI( descr, get_ftop(), i );
}
case 7: { /* FNSTSW m16 */
IRExpr* sw = get_FPU_sw();
- vassert(typeOfIRExpr(irbb->tyenv, sw) == Ity_I16);
+ vassert(typeOfIRExpr(irsb->tyenv, sw) == Ity_I16);
storeLE( mkexpr(addr), sw );
DIP("fnstsw %s\n", dis_buf);
break;
static void do_MMX_preamble ( void )
{
- Int i;
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
- IRExpr* zero = mkU32(0);
- IRExpr* tag1 = mkU8(1);
+ Int i;
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero = mkU32(0);
+ IRExpr* tag1 = mkU8(1);
put_ftop(zero);
for (i = 0; i < 8; i++)
stmt( IRStmt_PutI( descr, zero, i, tag1 ) );
static void do_EMMS_preamble ( void )
{
- Int i;
- IRArray* descr = mkIRArray( OFFB_FPTAGS, Ity_I8, 8 );
- IRExpr* zero = mkU32(0);
- IRExpr* tag0 = mkU8(0);
+ Int i;
+ IRRegArray* descr = mkIRRegArray( OFFB_FPTAGS, Ity_I8, 8 );
+ IRExpr* zero = mkU32(0);
+ IRExpr* tag0 = mkU8(0);
put_ftop(zero);
for (i = 0; i < 8; i++)
stmt( IRStmt_PutI( descr, zero, i, tag0 ) );
static void putMMXReg ( UInt archreg, IRExpr* e )
{
vassert(archreg < 8);
- vassert(typeOfIRExpr(irbb->tyenv,e) == Ity_I64);
+ vassert(typeOfIRExpr(irsb->tyenv,e) == Ity_I64);
stmt( IRStmt_Put( OFFB_FPREGS + 8 * archreg, e ) );
}
static void put_sse_roundingmode ( IRExpr* sseround )
{
- vassert(typeOfIRExpr(irbb->tyenv, sseround) == Ity_I32);
+ vassert(typeOfIRExpr(irsb->tyenv, sseround) == Ity_I32);
stmt( IRStmt_Put( OFFB_SSEROUND, sseround ) );
}
stmt( IRStmt_Put(OFFB_TILEN, mkU32(lineszB) ) );
- irbb->jumpkind = Ijk_TInval;
- irbb->next = mkU32(guest_EIP_bbstart+delta);
+ irsb->jumpkind = Ijk_TInval;
+ irsb->next = mkU32(guest_EIP_bbstart+delta);
dres.whatNext = Dis_StopHere;
DIP("clflush %s\n", dis_buf);
/* Disassemble a single instruction into IR. The instruction
is located in host memory at &guest_code[delta]. */
-DisResult disInstr_X86 ( IRBB* irbb_IN,
+DisResult disInstr_X86 ( IRSB* irsb_IN,
Bool put_IP,
Bool (*resteerOkFn) ( void*, Addr64 ),
void* callback_opaque,
Addr64 guest_IP,
VexArch guest_arch,
VexArchInfo* archinfo,
- VexMiscInfo* miscinfo,
+ VexAbiInfo* abiinfo,
Bool host_bigendian_IN )
{
DisResult dres;
/* Set globals (see top of this file) */
vassert(guest_arch == VexArchX86);
guest_code = guest_code_IN;
- irbb = irbb_IN;
+ irsb = irsb_IN;
host_is_bigendian = host_bigendian_IN;
guest_EIP_curr_instr = (Addr32)guest_IP;
guest_EIP_bbstart = (Addr32)toUInt(guest_IP - delta);
extern AMD64Instr* genSpill_AMD64 ( HReg rreg, Int offset, Bool );
extern AMD64Instr* genReload_AMD64 ( HReg rreg, Int offset, Bool );
extern void getAllocableRegs_AMD64 ( Int*, HReg** );
-extern HInstrArray* iselBB_AMD64 ( IRBB*, VexArch,
+extern HInstrArray* iselSB_AMD64 ( IRSB*, VexArch,
VexArchInfo*,
- VexMiscInfo* );
+ VexAbiInfo* );
#endif /* ndef __LIBVEX_HOST_AMD64_HDEFS_H */
Bool mightRequireFixedRegs ( IRExpr* e )
{
switch (e->tag) {
- case Iex_Tmp: case Iex_Const: case Iex_Get:
+ case Iex_RdTmp: case Iex_Const: case Iex_Get:
return False;
default:
return True;
offset. */
static
-AMD64AMode* genGuestArrayOffset ( ISelEnv* env, IRArray* descr,
+AMD64AMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
IRExpr* off, Int bias )
{
HReg tmp, roff;
switch (e->tag) {
/* --------- TEMP --------- */
- case Iex_Tmp: {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ case Iex_RdTmp: {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
/* --------- LOAD --------- */
vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
/* var */
- if (e->tag == Iex_Tmp) {
- HReg r64 = lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ HReg r64 = lookupIRTemp(env, e->Iex.RdTmp.tmp);
HReg dst = newVRegI(env);
addInstr(env, mk_iMOVsd_RR(r64,dst));
addInstr(env, AMD64Instr_Alu64R(Aalu_AND,AMD64RMI_Imm(1),dst));
//.. }
/* read 128-bit IRTemp */
- if (e->tag == Iex_Tmp) {
- lookupIRTemp128( rHi, rLo, env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTemp128( rHi, rLo, env, e->Iex.RdTmp.tmp);
return;
}
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_F32);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
vassert(e);
vassert(ty == Ity_F64);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Const) {
vassert(e);
vassert(ty == Ity_V128);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Get) {
}
/* --------- TMP --------- */
- case Ist_Tmp: {
- IRTemp tmp = stmt->Ist.Tmp.tmp;
+ case Ist_WrTmp: {
+ IRTemp tmp = stmt->Ist.WrTmp.tmp;
IRType ty = typeOfIRTemp(env->type_env, tmp);
if (ty == Ity_I64 || ty == Ity_I32
|| ty == Ity_I16 || ty == Ity_I8) {
- AMD64RMI* rmi = iselIntExpr_RMI(env, stmt->Ist.Tmp.data);
+ AMD64RMI* rmi = iselIntExpr_RMI(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, AMD64Instr_Alu64R(Aalu_MOV,rmi,dst));
return;
}
if (ty == Ity_I128) {
HReg rHi, rLo, dstHi, dstLo;
- iselInt128Expr(&rHi,&rLo, env, stmt->Ist.Tmp.data);
+ iselInt128Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
lookupIRTemp128( &dstHi, &dstLo, env, tmp);
addInstr(env, mk_iMOVsd_RR(rHi,dstHi) );
addInstr(env, mk_iMOVsd_RR(rLo,dstLo) );
return;
}
if (ty == Ity_I1) {
- AMD64CondCode cond = iselCondCode(env, stmt->Ist.Tmp.data);
+ AMD64CondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, AMD64Instr_Set64(cond, dst));
return;
}
if (ty == Ity_F64) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselDblExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, mk_vMOVsd_RR(src, dst));
return;
}
if (ty == Ity_F32) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselFltExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, mk_vMOVsd_RR(src, dst));
return;
}
if (ty == Ity_V128) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselVecExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselVecExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, mk_vMOVsd_RR(src, dst));
return;
}
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire BB to amd64 code. */
+/* Translate an entire SB to amd64 code. */
-HInstrArray* iselBB_AMD64 ( IRBB* bb, VexArch arch_host,
+HInstrArray* iselSB_AMD64 ( IRSB* bb, VexArch arch_host,
VexArchInfo* archinfo_host,
- VexMiscInfo* vmi/*UNUSED*/ )
+ VexAbiInfo* vbi/*UNUSED*/ )
{
Int i, j;
HReg hreg, hregHI;
extern ARMInstr* genSpill_ARM ( HReg rreg, Int offset );
extern ARMInstr* genReload_ARM ( HReg rreg, Int offset );
extern void getAllocableRegs_ARM ( Int*, HReg** );
-extern HInstrArray* iselBB_ARM ( IRBB* );
+extern HInstrArray* iselSB_ARM ( IRSB* );
#endif /* ndef __LIBVEX_ARMH_DEFS_H */
offset. */
static
-ARMAMode2* genGuestArrayOffset ( ISelEnv* env, IRArray* descr,
+ARMAMode2* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
IRExpr* off, Int bias )
{
HReg tmp, tmp2, roff;
/* --------- TMP --------- */
/* assign value to temporary */
- case Ist_Tmp: {
- IRTemp tmp = stmt->Ist.Tmp.tmp;
+ case Ist_WrTmp: {
+ IRTemp tmp = stmt->Ist.WrTmp.tmp;
IRType ty = typeOfIRTemp(env->type_env, tmp);
if (ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) {
- ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.Tmp.data);
+ ARMAMode1* am = iselIntExpr_AMode1(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, ARMInstr_DPInstr1(ARMalu_MOV,dst,am));
return;
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire BB to arm code. */
+/* Translate an entire SB to arm code. */
-HInstrArray* iselBB_ARM ( IRBB* bb )
+HInstrArray* iselSB_ARM ( IRSB* bb )
{
Int i, j;
extern PPCInstr* genSpill_PPC ( HReg rreg, UShort offsetB, Bool mode64 );
extern PPCInstr* genReload_PPC ( HReg rreg, UShort offsetB, Bool mode64 );
extern void getAllocableRegs_PPC ( Int*, HReg**, Bool mode64 );
-extern HInstrArray* iselBB_PPC ( IRBB*, VexArch,
+extern HInstrArray* iselSB_PPC ( IRSB*, VexArch,
VexArchInfo*,
- VexMiscInfo* );
+ VexAbiInfo* );
#endif /* ndef __LIBVEX_HOST_PPC_HDEFS_H */
IRExpr* previous_rm;
- VexMiscInfo* vmi;
+ VexAbiInfo* vbi;
}
ISelEnv;
bias, generate a PPCAMode pointing at the relevant piece of
guest state. */
static
-PPCAMode* genGuestArrayOffset ( ISelEnv* env, IRArray* descr,
+PPCAMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
IRExpr* off, Int bias )
{
HReg rtmp, roff;
Bool mightRequireFixedRegs ( IRExpr* e )
{
switch (e->tag) {
- case Iex_Tmp: case Iex_Const: case Iex_Get:
+ case Iex_RdTmp: case Iex_Const: case Iex_Get:
return False;
default:
return True;
/* Do we need to force use of an odd-even reg pair for 64-bit
args? */
Bool regalign_int64s
- = (!mode64) && env->vmi->host_ppc32_regalign_int64_args;
+ = (!mode64) && env->vbi->host_ppc32_regalign_int64_args;
/* Marshal args for a call and do the call.
/* Do we need to do anything? */
if (env->previous_rm
- && env->previous_rm->tag == Iex_Tmp
- && mode->tag == Iex_Tmp
- && env->previous_rm->Iex.Tmp.tmp == mode->Iex.Tmp.tmp) {
+ && env->previous_rm->tag == Iex_RdTmp
+ && mode->tag == Iex_RdTmp
+ && env->previous_rm->Iex.RdTmp.tmp == mode->Iex.RdTmp.tmp) {
/* no - setting it to what it was before. */
vassert(typeOfIRExpr(env->type_env, env->previous_rm) == Ity_I32);
return;
switch (e->tag) {
/* --------- TEMP --------- */
- case Iex_Tmp:
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
/* --------- LOAD --------- */
case Iex_Load: {
}
/* var */
- if (e->tag == Iex_Tmp) {
- HReg r_src = lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ HReg r_src = lookupIRTemp(env, e->Iex.RdTmp.tmp);
HReg src_masked = newVRegI(env);
addInstr(env,
PPCInstr_Alu(Palu_AND, src_masked,
vassert(typeOfIRExpr(env->type_env,e) == Ity_I128);
/* read 128-bit IRTemp */
- if (e->tag == Iex_Tmp) {
- lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
return;
}
}
/* read 64-bit IRTemp */
- if (e->tag == Iex_Tmp) {
- lookupIRTempPair( rHi, rLo, env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTempPair( rHi, rLo, env, e->Iex.RdTmp.tmp);
return;
}
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_F32);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
vassert(e);
vassert(ty == Ity_F64);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
/* --------- LITERAL --------- */
vassert(e);
vassert(ty == Ity_V128);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Get) {
}
/* --------- TMP --------- */
- case Ist_Tmp: {
- IRTemp tmp = stmt->Ist.Tmp.tmp;
+ case Ist_WrTmp: {
+ IRTemp tmp = stmt->Ist.WrTmp.tmp;
IRType ty = typeOfIRTemp(env->type_env, tmp);
if (ty == Ity_I8 || ty == Ity_I16 ||
ty == Ity_I32 || ((ty == Ity_I64) && mode64)) {
HReg r_dst = lookupIRTemp(env, tmp);
- HReg r_src = iselWordExpr_R(env, stmt->Ist.Tmp.data);
+ HReg r_src = iselWordExpr_R(env, stmt->Ist.WrTmp.data);
addInstr(env, mk_iMOVds_RR( r_dst, r_src ));
return;
}
if (!mode64 && ty == Ity_I64) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
- iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.Tmp.data);
+ iselInt64Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data);
lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
}
if (mode64 && ty == Ity_I128) {
HReg r_srcHi, r_srcLo, r_dstHi, r_dstLo;
- iselInt128Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.Tmp.data);
+ iselInt128Expr(&r_srcHi,&r_srcLo, env, stmt->Ist.WrTmp.data);
lookupIRTempPair( &r_dstHi, &r_dstLo, env, tmp);
addInstr(env, mk_iMOVds_RR(r_dstHi, r_srcHi) );
addInstr(env, mk_iMOVds_RR(r_dstLo, r_srcLo) );
return;
}
if (ty == Ity_I1) {
- PPCCondCode cond = iselCondCode(env, stmt->Ist.Tmp.data);
+ PPCCondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
HReg r_dst = lookupIRTemp(env, tmp);
addInstr(env, PPCInstr_Set(cond, r_dst));
return;
}
if (ty == Ity_F64) {
HReg fr_dst = lookupIRTemp(env, tmp);
- HReg fr_src = iselDblExpr(env, stmt->Ist.Tmp.data);
+ HReg fr_src = iselDblExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src));
return;
}
if (ty == Ity_F32) {
HReg fr_dst = lookupIRTemp(env, tmp);
- HReg fr_src = iselFltExpr(env, stmt->Ist.Tmp.data);
+ HReg fr_src = iselFltExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, PPCInstr_FpUnary(Pfp_MOV, fr_dst, fr_src));
return;
}
if (ty == Ity_V128) {
HReg v_dst = lookupIRTemp(env, tmp);
- HReg v_src = iselVecExpr(env, stmt->Ist.Tmp.data);
+ HReg v_src = iselVecExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, PPCInstr_AvUnary(Pav_MOV, v_dst, v_src));
return;
}
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire BB to ppc code. */
+/* Translate an entire BS to ppc code. */
-HInstrArray* iselBB_PPC ( IRBB* bb, VexArch arch_host,
+HInstrArray* iselSB_PPC ( IRSB* bb, VexArch arch_host,
VexArchInfo* archinfo_host,
- VexMiscInfo* vmi )
+ VexAbiInfo* vbi )
{
Int i, j;
HReg hreg, hregHI;
/* and finally ... */
env->hwcaps = hwcaps_host;
env->previous_rm = NULL;
- env->vmi = vmi;
+ env->vbi = vbi;
/* For each IR temporary, allocate a suitably-kinded virtual
register. */
extern X86Instr* genSpill_X86 ( HReg rreg, Int offset, Bool );
extern X86Instr* genReload_X86 ( HReg rreg, Int offset, Bool );
extern void getAllocableRegs_X86 ( Int*, HReg** );
-extern HInstrArray* iselBB_X86 ( IRBB*, VexArch,
+extern HInstrArray* iselSB_X86 ( IRSB*, VexArch,
VexArchInfo*,
- VexMiscInfo* );
+ VexAbiInfo* );
#endif /* ndef __LIBVEX_HOST_X86_HDEFS_H */
Bool mightRequireFixedRegs ( IRExpr* e )
{
switch (e->tag) {
- case Iex_Tmp: case Iex_Const: case Iex_Get:
+ case Iex_RdTmp: case Iex_Const: case Iex_Get:
return False;
default:
return True;
offset. */
static
-X86AMode* genGuestArrayOffset ( ISelEnv* env, IRArray* descr,
+X86AMode* genGuestArrayOffset ( ISelEnv* env, IRRegArray* descr,
IRExpr* off, Int bias )
{
HReg tmp, roff;
switch (e->tag) {
/* --------- TEMP --------- */
- case Iex_Tmp: {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ case Iex_RdTmp: {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
/* --------- LOAD --------- */
vassert(typeOfIRExpr(env->type_env,e) == Ity_I1);
/* var */
- if (e->tag == Iex_Tmp) {
- HReg r32 = lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ HReg r32 = lookupIRTemp(env, e->Iex.RdTmp.tmp);
/* Test32 doesn't modify r32; so this is OK. */
addInstr(env, X86Instr_Test32(1,r32));
return Xcc_NZ;
}
/* read 64-bit IRTemp */
- if (e->tag == Iex_Tmp) {
- lookupIRTemp64( rHi, rLo, env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ lookupIRTemp64( rHi, rLo, env, e->Iex.RdTmp.tmp);
return;
}
IRType ty = typeOfIRExpr(env->type_env,e);
vassert(ty == Ity_F32);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Load && e->Iex.Load.end == Iend_LE) {
vassert(e);
vassert(ty == Ity_F64);
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Const) {
REQUIRE_SSE1;
- if (e->tag == Iex_Tmp) {
- return lookupIRTemp(env, e->Iex.Tmp.tmp);
+ if (e->tag == Iex_RdTmp) {
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
}
if (e->tag == Iex_Get) {
}
/* --------- TMP --------- */
- case Ist_Tmp: {
- IRTemp tmp = stmt->Ist.Tmp.tmp;
+ case Ist_WrTmp: {
+ IRTemp tmp = stmt->Ist.WrTmp.tmp;
IRType ty = typeOfIRTemp(env->type_env, tmp);
if (ty == Ity_I32 || ty == Ity_I16 || ty == Ity_I8) {
- X86RMI* rmi = iselIntExpr_RMI(env, stmt->Ist.Tmp.data);
+ X86RMI* rmi = iselIntExpr_RMI(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, X86Instr_Alu32R(Xalu_MOV,rmi,dst));
return;
}
if (ty == Ity_I64) {
HReg rHi, rLo, dstHi, dstLo;
- iselInt64Expr(&rHi,&rLo, env, stmt->Ist.Tmp.data);
+ iselInt64Expr(&rHi,&rLo, env, stmt->Ist.WrTmp.data);
lookupIRTemp64( &dstHi, &dstLo, env, tmp);
addInstr(env, mk_iMOVsd_RR(rHi,dstHi) );
addInstr(env, mk_iMOVsd_RR(rLo,dstLo) );
return;
}
if (ty == Ity_I1) {
- X86CondCode cond = iselCondCode(env, stmt->Ist.Tmp.data);
+ X86CondCode cond = iselCondCode(env, stmt->Ist.WrTmp.data);
HReg dst = lookupIRTemp(env, tmp);
addInstr(env, X86Instr_Set32(cond, dst));
return;
}
if (ty == Ity_F64) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselDblExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselDblExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, X86Instr_FpUnary(Xfp_MOV,src,dst));
return;
}
if (ty == Ity_F32) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselFltExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselFltExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, X86Instr_FpUnary(Xfp_MOV,src,dst));
return;
}
if (ty == Ity_V128) {
HReg dst = lookupIRTemp(env, tmp);
- HReg src = iselVecExpr(env, stmt->Ist.Tmp.data);
+ HReg src = iselVecExpr(env, stmt->Ist.WrTmp.data);
addInstr(env, mk_vMOVsd_RR(src,dst));
return;
}
/*--- Insn selector top-level ---*/
/*---------------------------------------------------------*/
-/* Translate an entire BB to x86 code. */
+/* Translate an entire SB to x86 code. */
-HInstrArray* iselBB_X86 ( IRBB* bb, VexArch arch_host,
+HInstrArray* iselSB_X86 ( IRSB* bb, VexArch arch_host,
VexArchInfo* archinfo_host,
- VexMiscInfo* vmi/*UNUSED*/ )
+ VexAbiInfo* vbi/*UNUSED*/ )
{
Int i, j;
HReg hreg, hregHI;
vex_printf("{%p}", (void*)ce->addr);
}
-void ppIRArray ( IRArray* arr )
+void ppIRRegArray ( IRRegArray* arr )
{
vex_printf("(%d:%dx", arr->base, arr->nElems);
ppIRType(arr->elemTy);
break;
case Iex_GetI:
vex_printf( "GETI" );
- ppIRArray(e->Iex.GetI.descr);
+ ppIRRegArray(e->Iex.GetI.descr);
vex_printf("[");
ppIRExpr(e->Iex.GetI.ix);
vex_printf(",%d]", e->Iex.GetI.bias);
break;
- case Iex_Tmp:
- ppIRTemp(e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ ppIRTemp(e->Iex.RdTmp.tmp);
break;
case Iex_Qop:
ppIROp(e->Iex.Qop.op);
break;
case Ist_PutI:
vex_printf( "PUTI" );
- ppIRArray(s->Ist.PutI.descr);
+ ppIRRegArray(s->Ist.PutI.descr);
vex_printf("[");
ppIRExpr(s->Ist.PutI.ix);
vex_printf(",%d] = ", s->Ist.PutI.bias);
ppIRExpr(s->Ist.PutI.data);
break;
- case Ist_Tmp:
- ppIRTemp(s->Ist.Tmp.tmp);
+ case Ist_WrTmp:
+ ppIRTemp(s->Ist.WrTmp.tmp);
vex_printf( " = " );
- ppIRExpr(s->Ist.Tmp.data);
+ ppIRExpr(s->Ist.WrTmp.data);
break;
case Ist_Store:
vex_printf( "ST%s(", s->Ist.Store.end==Iend_LE ? "le" : "be" );
vex_printf( "\n");
}
-void ppIRBB ( IRBB* bb )
+void ppIRSB ( IRSB* bb )
{
Int i;
- vex_printf("IRBB {\n");
+ vex_printf("IRSB {\n");
ppIRTypeEnv(bb->tyenv);
vex_printf("\n");
for (i = 0; i < bb->stmts_used; i++) {
}
-/* Constructors -- IRArray */
+/* Constructors -- IRRegArray */
-IRArray* mkIRArray ( Int base, IRType elemTy, Int nElems )
+IRRegArray* mkIRRegArray ( Int base, IRType elemTy, Int nElems )
{
- IRArray* arr = LibVEX_Alloc(sizeof(IRArray));
- arr->base = base;
- arr->elemTy = elemTy;
- arr->nElems = nElems;
+ IRRegArray* arr = LibVEX_Alloc(sizeof(IRRegArray));
+ arr->base = base;
+ arr->elemTy = elemTy;
+ arr->nElems = nElems;
vassert(!(arr->base < 0 || arr->base > 10000 /* somewhat arbitrary */));
vassert(!(arr->elemTy == Ity_I1));
vassert(!(arr->nElems <= 0 || arr->nElems > 500 /* somewhat arbitrary */));
e->Iex.Get.ty = ty;
return e;
}
-IRExpr* IRExpr_GetI ( IRArray* descr, IRExpr* ix, Int bias ) {
+IRExpr* IRExpr_GetI ( IRRegArray* descr, IRExpr* ix, Int bias ) {
IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
e->tag = Iex_GetI;
e->Iex.GetI.descr = descr;
e->Iex.GetI.bias = bias;
return e;
}
-IRExpr* IRExpr_Tmp ( IRTemp tmp ) {
- IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
- e->tag = Iex_Tmp;
- e->Iex.Tmp.tmp = tmp;
+IRExpr* IRExpr_RdTmp ( IRTemp tmp ) {
+ IRExpr* e = LibVEX_Alloc(sizeof(IRExpr));
+ e->tag = Iex_RdTmp;
+ e->Iex.RdTmp.tmp = tmp;
return e;
}
IRExpr* IRExpr_Qop ( IROp op, IRExpr* arg1, IRExpr* arg2,
s->Ist.Put.data = data;
return s;
}
-IRStmt* IRStmt_PutI ( IRArray* descr, IRExpr* ix,
+IRStmt* IRStmt_PutI ( IRRegArray* descr, IRExpr* ix,
Int bias, IRExpr* data ) {
IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
s->tag = Ist_PutI;
s->Ist.PutI.data = data;
return s;
}
-IRStmt* IRStmt_Tmp ( IRTemp tmp, IRExpr* data ) {
- IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
- s->tag = Ist_Tmp;
- s->Ist.Tmp.tmp = tmp;
- s->Ist.Tmp.data = data;
+IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data ) {
+ IRStmt* s = LibVEX_Alloc(sizeof(IRStmt));
+ s->tag = Ist_WrTmp;
+ s->Ist.WrTmp.tmp = tmp;
+ s->Ist.WrTmp.data = data;
return s;
}
IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data ) {
}
-/* Constructors -- IRBB */
+/* Constructors -- IRSB */
-IRBB* emptyIRBB ( void )
+IRSB* emptyIRSB ( void )
{
- IRBB* bb = LibVEX_Alloc(sizeof(IRBB));
+ IRSB* bb = LibVEX_Alloc(sizeof(IRSB));
bb->tyenv = emptyIRTypeEnv();
bb->stmts_used = 0;
bb->stmts_size = 8;
/* Shallow copy of an IRExpr vector */
-IRExpr** sopyIRExprVec ( IRExpr** vec )
+IRExpr** shallowCopyIRExprVec ( IRExpr** vec )
{
Int i;
IRExpr** newvec;
/* Deep copy of an IRExpr vector */
-IRExpr** dopyIRExprVec ( IRExpr** vec )
+IRExpr** deepCopyIRExprVec ( IRExpr** vec )
{
Int i;
- IRExpr** newvec = sopyIRExprVec( vec );
+ IRExpr** newvec = shallowCopyIRExprVec( vec );
for (i = 0; newvec[i]; i++)
- newvec[i] = dopyIRExpr(newvec[i]);
+ newvec[i] = deepCopyIRExpr(newvec[i]);
return newvec;
}
/* Deep copy constructors for all heap-allocated IR types follow. */
-IRConst* dopyIRConst ( IRConst* c )
+IRConst* deepCopyIRConst ( IRConst* c )
{
switch (c->tag) {
case Ico_U1: return IRConst_U1(c->Ico.U1);
case Ico_F64: return IRConst_F64(c->Ico.F64);
case Ico_F64i: return IRConst_F64i(c->Ico.F64i);
case Ico_V128: return IRConst_V128(c->Ico.V128);
- default: vpanic("dopyIRConst");
+ default: vpanic("deepCopyIRConst");
}
}
-IRCallee* dopyIRCallee ( IRCallee* ce )
+IRCallee* deepCopyIRCallee ( IRCallee* ce )
{
IRCallee* ce2 = mkIRCallee(ce->regparms, ce->name, ce->addr);
ce2->mcx_mask = ce->mcx_mask;
return ce2;
}
-IRArray* dopyIRArray ( IRArray* d )
+IRRegArray* deepCopyIRRegArray ( IRRegArray* d )
{
- return mkIRArray(d->base, d->elemTy, d->nElems);
+ return mkIRRegArray(d->base, d->elemTy, d->nElems);
}
-IRExpr* dopyIRExpr ( IRExpr* e )
+IRExpr* deepCopyIRExpr ( IRExpr* e )
{
switch (e->tag) {
case Iex_Get:
return IRExpr_Get(e->Iex.Get.offset, e->Iex.Get.ty);
case Iex_GetI:
- return IRExpr_GetI(dopyIRArray(e->Iex.GetI.descr),
- dopyIRExpr(e->Iex.GetI.ix),
+ return IRExpr_GetI(deepCopyIRRegArray(e->Iex.GetI.descr),
+ deepCopyIRExpr(e->Iex.GetI.ix),
e->Iex.GetI.bias);
- case Iex_Tmp:
- return IRExpr_Tmp(e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ return IRExpr_RdTmp(e->Iex.RdTmp.tmp);
case Iex_Qop:
return IRExpr_Qop(e->Iex.Qop.op,
- dopyIRExpr(e->Iex.Qop.arg1),
- dopyIRExpr(e->Iex.Qop.arg2),
- dopyIRExpr(e->Iex.Qop.arg3),
- dopyIRExpr(e->Iex.Qop.arg4));
+ deepCopyIRExpr(e->Iex.Qop.arg1),
+ deepCopyIRExpr(e->Iex.Qop.arg2),
+ deepCopyIRExpr(e->Iex.Qop.arg3),
+ deepCopyIRExpr(e->Iex.Qop.arg4));
case Iex_Triop:
return IRExpr_Triop(e->Iex.Triop.op,
- dopyIRExpr(e->Iex.Triop.arg1),
- dopyIRExpr(e->Iex.Triop.arg2),
- dopyIRExpr(e->Iex.Triop.arg3));
+ deepCopyIRExpr(e->Iex.Triop.arg1),
+ deepCopyIRExpr(e->Iex.Triop.arg2),
+ deepCopyIRExpr(e->Iex.Triop.arg3));
case Iex_Binop:
return IRExpr_Binop(e->Iex.Binop.op,
- dopyIRExpr(e->Iex.Binop.arg1),
- dopyIRExpr(e->Iex.Binop.arg2));
+ deepCopyIRExpr(e->Iex.Binop.arg1),
+ deepCopyIRExpr(e->Iex.Binop.arg2));
case Iex_Unop:
return IRExpr_Unop(e->Iex.Unop.op,
- dopyIRExpr(e->Iex.Unop.arg));
+ deepCopyIRExpr(e->Iex.Unop.arg));
case Iex_Load:
return IRExpr_Load(e->Iex.Load.end,
e->Iex.Load.ty,
- dopyIRExpr(e->Iex.Load.addr));
+ deepCopyIRExpr(e->Iex.Load.addr));
case Iex_Const:
- return IRExpr_Const(dopyIRConst(e->Iex.Const.con));
+ return IRExpr_Const(deepCopyIRConst(e->Iex.Const.con));
case Iex_CCall:
- return IRExpr_CCall(dopyIRCallee(e->Iex.CCall.cee),
+ return IRExpr_CCall(deepCopyIRCallee(e->Iex.CCall.cee),
e->Iex.CCall.retty,
- dopyIRExprVec(e->Iex.CCall.args));
+ deepCopyIRExprVec(e->Iex.CCall.args));
case Iex_Mux0X:
- return IRExpr_Mux0X(dopyIRExpr(e->Iex.Mux0X.cond),
- dopyIRExpr(e->Iex.Mux0X.expr0),
- dopyIRExpr(e->Iex.Mux0X.exprX));
+ return IRExpr_Mux0X(deepCopyIRExpr(e->Iex.Mux0X.cond),
+ deepCopyIRExpr(e->Iex.Mux0X.expr0),
+ deepCopyIRExpr(e->Iex.Mux0X.exprX));
default:
- vpanic("dopyIRExpr");
+ vpanic("deepCopyIRExpr");
}
}
-IRDirty* dopyIRDirty ( IRDirty* d )
+IRDirty* deepCopyIRDirty ( IRDirty* d )
{
Int i;
IRDirty* d2 = emptyIRDirty();
- d2->cee = dopyIRCallee(d->cee);
- d2->guard = dopyIRExpr(d->guard);
- d2->args = dopyIRExprVec(d->args);
+ d2->cee = deepCopyIRCallee(d->cee);
+ d2->guard = deepCopyIRExpr(d->guard);
+ d2->args = deepCopyIRExprVec(d->args);
d2->tmp = d->tmp;
d2->mFx = d->mFx;
- d2->mAddr = d->mAddr==NULL ? NULL : dopyIRExpr(d->mAddr);
+ d2->mAddr = d->mAddr==NULL ? NULL : deepCopyIRExpr(d->mAddr);
d2->mSize = d->mSize;
d2->needsBBP = d->needsBBP;
d2->nFxState = d->nFxState;
return d2;
}
-IRStmt* dopyIRStmt ( IRStmt* s )
+IRStmt* deepCopyIRStmt ( IRStmt* s )
{
switch (s->tag) {
case Ist_NoOp:
return IRStmt_NoOp();
case Ist_AbiHint:
- return IRStmt_AbiHint(dopyIRExpr(s->Ist.AbiHint.base),
+ return IRStmt_AbiHint(deepCopyIRExpr(s->Ist.AbiHint.base),
s->Ist.AbiHint.len);
case Ist_IMark:
return IRStmt_IMark(s->Ist.IMark.addr, s->Ist.IMark.len);
case Ist_Put:
return IRStmt_Put(s->Ist.Put.offset,
- dopyIRExpr(s->Ist.Put.data));
+ deepCopyIRExpr(s->Ist.Put.data));
case Ist_PutI:
- return IRStmt_PutI(dopyIRArray(s->Ist.PutI.descr),
- dopyIRExpr(s->Ist.PutI.ix),
+ return IRStmt_PutI(deepCopyIRRegArray(s->Ist.PutI.descr),
+ deepCopyIRExpr(s->Ist.PutI.ix),
s->Ist.PutI.bias,
- dopyIRExpr(s->Ist.PutI.data));
- case Ist_Tmp:
- return IRStmt_Tmp(s->Ist.Tmp.tmp,
- dopyIRExpr(s->Ist.Tmp.data));
+ deepCopyIRExpr(s->Ist.PutI.data));
+ case Ist_WrTmp:
+ return IRStmt_WrTmp(s->Ist.WrTmp.tmp,
+ deepCopyIRExpr(s->Ist.WrTmp.data));
case Ist_Store:
return IRStmt_Store(s->Ist.Store.end,
- dopyIRExpr(s->Ist.Store.addr),
- dopyIRExpr(s->Ist.Store.data));
+ deepCopyIRExpr(s->Ist.Store.addr),
+ deepCopyIRExpr(s->Ist.Store.data));
case Ist_Dirty:
- return IRStmt_Dirty(dopyIRDirty(s->Ist.Dirty.details));
+ return IRStmt_Dirty(deepCopyIRDirty(s->Ist.Dirty.details));
case Ist_MFence:
return IRStmt_MFence();
case Ist_Exit:
- return IRStmt_Exit(dopyIRExpr(s->Ist.Exit.guard),
+ return IRStmt_Exit(deepCopyIRExpr(s->Ist.Exit.guard),
s->Ist.Exit.jk,
- dopyIRConst(s->Ist.Exit.dst));
+ deepCopyIRConst(s->Ist.Exit.dst));
default:
- vpanic("dopyIRStmt");
+ vpanic("deepCopyIRStmt");
}
}
-IRTypeEnv* dopyIRTypeEnv ( IRTypeEnv* src )
+IRTypeEnv* deepCopyIRTypeEnv ( IRTypeEnv* src )
{
Int i;
IRTypeEnv* dst = LibVEX_Alloc(sizeof(IRTypeEnv));
return dst;
}
-IRBB* dopyIRBB ( IRBB* bb )
+IRSB* deepCopyIRSB ( IRSB* bb )
{
Int i;
IRStmt** sts2;
- IRBB* bb2 = dopyIRBBExceptStmts(bb);
+ IRSB* bb2 = deepCopyIRSBExceptStmts(bb);
bb2->stmts_used = bb2->stmts_size = bb->stmts_used;
sts2 = LibVEX_Alloc(bb2->stmts_used * sizeof(IRStmt*));
for (i = 0; i < bb2->stmts_used; i++)
- sts2[i] = dopyIRStmt(bb->stmts[i]);
+ sts2[i] = deepCopyIRStmt(bb->stmts[i]);
bb2->stmts = sts2;
return bb2;
}
-IRBB* dopyIRBBExceptStmts ( IRBB* bb )
+IRSB* deepCopyIRSBExceptStmts ( IRSB* bb )
{
- IRBB* bb2 = emptyIRBB();
- bb2->tyenv = dopyIRTypeEnv(bb->tyenv);
- bb2->next = dopyIRExpr(bb->next);
+ IRSB* bb2 = emptyIRSB();
+ bb2->tyenv = deepCopyIRTypeEnv(bb->tyenv);
+ bb2->next = deepCopyIRExpr(bb->next);
bb2->jumpkind = bb->jumpkind;
return bb2;
}
/*--- Helper functions for the IR -- IR Basic Blocks ---*/
/*---------------------------------------------------------------*/
-void addStmtToIRBB ( IRBB* bb, IRStmt* st )
+void addStmtToIRSB ( IRSB* bb, IRStmt* st )
{
Int i;
if (bb->stmts_used == bb->stmts_size) {
return e->Iex.Get.ty;
case Iex_GetI:
return e->Iex.GetI.descr->elemTy;
- case Iex_Tmp:
- return typeOfIRTemp(tyenv, e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ return typeOfIRTemp(tyenv, e->Iex.RdTmp.tmp);
case Iex_Const:
return typeOfIRConst(e->Iex.Const.con);
case Iex_Qop:
/* Relies on:
inline static Bool isAtom ( IRExpr* e ) {
- return e->tag == Iex_Tmp || e->tag == Iex_Const;
+ return e->tag == Iex_RdTmp || e->tag == Iex_Const;
}
*/
case Ist_PutI:
return toBool( isIRAtom(st->Ist.PutI.ix)
&& isIRAtom(st->Ist.PutI.data) );
- case Ist_Tmp:
+ case Ist_WrTmp:
/* This is the only interesting case. The RHS can be any
expression, *but* all its subexpressions *must* be
atoms. */
- e = st->Ist.Tmp.data;
+ e = st->Ist.WrTmp.data;
switch (e->tag) {
case Iex_Binder: return True;
case Iex_Get: return True;
case Iex_GetI: return isIRAtom(e->Iex.GetI.ix);
- case Iex_Tmp: return True;
+ case Iex_RdTmp: return True;
case Iex_Qop: return toBool(
isIRAtom(e->Iex.Qop.arg1)
&& isIRAtom(e->Iex.Qop.arg2)
static
__attribute((noreturn))
-void sanityCheckFail ( IRBB* bb, IRStmt* stmt, HChar* what )
+void sanityCheckFail ( IRSB* bb, IRStmt* stmt, HChar* what )
{
vex_printf("\nIR SANITY CHECK FAILURE\n\n");
- ppIRBB(bb);
+ ppIRSB(bb);
if (stmt) {
vex_printf("\nIN STATEMENT:\n\n");
ppIRStmt(stmt);
vpanic("sanityCheckFail: exiting due to bad IR");
}
-static Bool saneIRArray ( IRArray* arr )
+static Bool saneIRRegArray ( IRRegArray* arr )
{
if (arr->base < 0 || arr->base > 10000 /* somewhat arbitrary */)
return False;
def_count is zero. */
static
-void useBeforeDef_Temp ( IRBB* bb, IRStmt* stmt, IRTemp tmp, Int* def_counts )
+void useBeforeDef_Temp ( IRSB* bb, IRStmt* stmt, IRTemp tmp, Int* def_counts )
{
if (tmp < 0 || tmp >= bb->tyenv->types_used)
sanityCheckFail(bb,stmt, "out of range Temp in IRExpr");
}
static
-void useBeforeDef_Expr ( IRBB* bb, IRStmt* stmt, IRExpr* expr, Int* def_counts )
+void useBeforeDef_Expr ( IRSB* bb, IRStmt* stmt, IRExpr* expr, Int* def_counts )
{
Int i;
switch (expr->tag) {
case Iex_GetI:
useBeforeDef_Expr(bb,stmt,expr->Iex.GetI.ix,def_counts);
break;
- case Iex_Tmp:
- useBeforeDef_Temp(bb,stmt,expr->Iex.Tmp.tmp,def_counts);
+ case Iex_RdTmp:
+ useBeforeDef_Temp(bb,stmt,expr->Iex.RdTmp.tmp,def_counts);
break;
case Iex_Qop:
useBeforeDef_Expr(bb,stmt,expr->Iex.Qop.arg1,def_counts);
}
static
-void useBeforeDef_Stmt ( IRBB* bb, IRStmt* stmt, Int* def_counts )
+void useBeforeDef_Stmt ( IRSB* bb, IRStmt* stmt, Int* def_counts )
{
Int i;
IRDirty* d;
useBeforeDef_Expr(bb,stmt,stmt->Ist.PutI.ix,def_counts);
useBeforeDef_Expr(bb,stmt,stmt->Ist.PutI.data,def_counts);
break;
- case Ist_Tmp:
- useBeforeDef_Expr(bb,stmt,stmt->Ist.Tmp.data,def_counts);
+ case Ist_WrTmp:
+ useBeforeDef_Expr(bb,stmt,stmt->Ist.WrTmp.data,def_counts);
break;
case Ist_Store:
useBeforeDef_Expr(bb,stmt,stmt->Ist.Store.addr,def_counts);
}
static
-void tcExpr ( IRBB* bb, IRStmt* stmt, IRExpr* expr, IRType gWordTy )
+void tcExpr ( IRSB* bb, IRStmt* stmt, IRExpr* expr, IRType gWordTy )
{
Int i;
IRType t_dst, t_arg1, t_arg2, t_arg3, t_arg4;
IRTypeEnv* tyenv = bb->tyenv;
switch (expr->tag) {
case Iex_Get:
- case Iex_Tmp:
+ case Iex_RdTmp:
break;
case Iex_GetI:
tcExpr(bb,stmt, expr->Iex.GetI.ix, gWordTy );
if (typeOfIRExpr(tyenv,expr->Iex.GetI.ix) != Ity_I32)
sanityCheckFail(bb,stmt,"IRExpr.GetI.ix: not :: Ity_I32");
- if (!saneIRArray(expr->Iex.GetI.descr))
+ if (!saneIRRegArray(expr->Iex.GetI.descr))
sanityCheckFail(bb,stmt,"IRExpr.GetI.descr: invalid descr");
break;
case Iex_Qop: {
static
-void tcStmt ( IRBB* bb, IRStmt* stmt, IRType gWordTy )
+void tcStmt ( IRSB* bb, IRStmt* stmt, IRType gWordTy )
{
Int i;
IRDirty* d;
sanityCheckFail(bb,stmt,"IRStmt.PutI.data: data ty != elem ty");
if (typeOfIRExpr(tyenv,stmt->Ist.PutI.ix) != Ity_I32)
sanityCheckFail(bb,stmt,"IRStmt.PutI.ix: not :: Ity_I32");
- if (!saneIRArray(stmt->Ist.PutI.descr))
+ if (!saneIRRegArray(stmt->Ist.PutI.descr))
sanityCheckFail(bb,stmt,"IRStmt.PutI.descr: invalid descr");
break;
- case Ist_Tmp:
- tcExpr( bb, stmt, stmt->Ist.Tmp.data, gWordTy );
- if (typeOfIRTemp(tyenv, stmt->Ist.Tmp.tmp)
- != typeOfIRExpr(tyenv, stmt->Ist.Tmp.data))
+ case Ist_WrTmp:
+ tcExpr( bb, stmt, stmt->Ist.WrTmp.data, gWordTy );
+ if (typeOfIRTemp(tyenv, stmt->Ist.WrTmp.tmp)
+ != typeOfIRExpr(tyenv, stmt->Ist.WrTmp.data))
sanityCheckFail(bb,stmt,"IRStmt.Put.Tmp: tmp and expr do not match");
break;
case Ist_Store:
}
}
-void sanityCheckIRBB ( IRBB* bb, HChar* caller,
+void sanityCheckIRSB ( IRSB* bb, HChar* caller,
Bool require_flat, IRType guest_word_size )
{
Int i;
if (bb->stmts_used < 0 || bb->stmts_size < 8
|| bb->stmts_used > bb->stmts_size)
/* this BB is so strange we can't even print it */
- vpanic("sanityCheckIRBB: stmts array limits wierd");
+ vpanic("sanityCheckIRSB: stmts array limits wierd");
/* Ensure each temp has a plausible type. */
for (i = 0; i < n_temps; i++) {
stmt = bb->stmts[i];
useBeforeDef_Stmt(bb,stmt,def_counts);
- if (stmt->tag == Ist_Tmp) {
- if (stmt->Ist.Tmp.tmp < 0 || stmt->Ist.Tmp.tmp >= n_temps)
+ if (stmt->tag == Ist_WrTmp) {
+ if (stmt->Ist.WrTmp.tmp < 0 || stmt->Ist.WrTmp.tmp >= n_temps)
sanityCheckFail(bb, stmt,
"IRStmt.Tmp: destination tmp is out of range");
- def_counts[stmt->Ist.Tmp.tmp]++;
- if (def_counts[stmt->Ist.Tmp.tmp] > 1)
+ def_counts[stmt->Ist.WrTmp.tmp]++;
+ if (def_counts[stmt->Ist.WrTmp.tmp] > 1)
sanityCheckFail(bb, stmt,
"IRStmt.Tmp: destination tmp is assigned more than once");
}
}
}
-Bool eqIRArray ( IRArray* descr1, IRArray* descr2 )
+Bool eqIRRegArray ( IRRegArray* descr1, IRRegArray* descr2 )
{
return toBool( descr1->base == descr2->base
&& descr1->elemTy == descr2->elemTy
{
vassert(isIRAtom(a1));
vassert(isIRAtom(a2));
- if (a1->tag == Iex_Tmp && a2->tag == Iex_Tmp)
- return toBool(a1->Iex.Tmp.tmp == a2->Iex.Tmp.tmp);
+ if (a1->tag == Iex_RdTmp && a2->tag == Iex_RdTmp)
+ return toBool(a1->Iex.RdTmp.tmp == a2->Iex.RdTmp.tmp);
if (a1->tag == Iex_Const && a2->tag == Iex_Const)
return eqIRConst(a1->Iex.Const.con, a2->Iex.Const.con);
return False;
the same value, after having appended extra IRTemp assignments to
the end of 'bb'. */
-static IRExpr* flatten_Expr ( IRBB* bb, IRExpr* ex )
+static IRExpr* flatten_Expr ( IRSB* bb, IRExpr* ex )
{
Int i;
IRExpr** newargs;
case Iex_GetI:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_GetI(ex->Iex.GetI.descr,
flatten_Expr(bb, ex->Iex.GetI.ix),
ex->Iex.GetI.bias)));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Get:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb,
- IRStmt_Tmp(t1, ex));
- return IRExpr_Tmp(t1);
+ addStmtToIRSB(bb,
+ IRStmt_WrTmp(t1, ex));
+ return IRExpr_RdTmp(t1);
case Iex_Qop:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Qop(ex->Iex.Qop.op,
flatten_Expr(bb, ex->Iex.Qop.arg1),
flatten_Expr(bb, ex->Iex.Qop.arg2),
flatten_Expr(bb, ex->Iex.Qop.arg3),
flatten_Expr(bb, ex->Iex.Qop.arg4))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Triop:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Triop(ex->Iex.Triop.op,
flatten_Expr(bb, ex->Iex.Triop.arg1),
flatten_Expr(bb, ex->Iex.Triop.arg2),
flatten_Expr(bb, ex->Iex.Triop.arg3))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Binop:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Binop(ex->Iex.Binop.op,
flatten_Expr(bb, ex->Iex.Binop.arg1),
flatten_Expr(bb, ex->Iex.Binop.arg2))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Unop:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Unop(ex->Iex.Unop.op,
flatten_Expr(bb, ex->Iex.Unop.arg))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Load:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Load(ex->Iex.Load.end,
ex->Iex.Load.ty,
flatten_Expr(bb, ex->Iex.Load.addr))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_CCall:
- newargs = sopyIRExprVec(ex->Iex.CCall.args);
+ newargs = shallowCopyIRExprVec(ex->Iex.CCall.args);
for (i = 0; newargs[i]; i++)
newargs[i] = flatten_Expr(bb, newargs[i]);
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_CCall(ex->Iex.CCall.cee,
ex->Iex.CCall.retty,
newargs)));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Mux0X:
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Mux0X(flatten_Expr(bb, ex->Iex.Mux0X.cond),
flatten_Expr(bb, ex->Iex.Mux0X.expr0),
flatten_Expr(bb, ex->Iex.Mux0X.exprX))));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
case Iex_Const:
/* Lift F64i constants out onto temps so they can be CSEd
later. */
if (ex->Iex.Const.con->tag == Ico_F64i) {
t1 = newIRTemp(bb->tyenv, ty);
- addStmtToIRBB(bb, IRStmt_Tmp(t1,
+ addStmtToIRSB(bb, IRStmt_WrTmp(t1,
IRExpr_Const(ex->Iex.Const.con)));
- return IRExpr_Tmp(t1);
+ return IRExpr_RdTmp(t1);
} else {
/* Leave all other constants alone. */
return ex;
}
- case Iex_Tmp:
+ case Iex_RdTmp:
return ex;
default:
/* Append a completely flattened form of 'st' to the end of 'bb'. */
-static void flatten_Stmt ( IRBB* bb, IRStmt* st )
+static void flatten_Stmt ( IRSB* bb, IRStmt* st )
{
Int i;
IRExpr *e1, *e2;
if (isIRAtom(st->Ist.Put.data)) {
/* optimisation to reduce the amount of heap wasted
by the flattener */
- addStmtToIRBB(bb, st);
+ addStmtToIRSB(bb, st);
} else {
/* general case, always correct */
e1 = flatten_Expr(bb, st->Ist.Put.data);
- addStmtToIRBB(bb, IRStmt_Put(st->Ist.Put.offset, e1));
+ addStmtToIRSB(bb, IRStmt_Put(st->Ist.Put.offset, e1));
}
break;
case Ist_PutI:
e1 = flatten_Expr(bb, st->Ist.PutI.ix);
e2 = flatten_Expr(bb, st->Ist.PutI.data);
- addStmtToIRBB(bb, IRStmt_PutI(st->Ist.PutI.descr,
+ addStmtToIRSB(bb, IRStmt_PutI(st->Ist.PutI.descr,
e1,
st->Ist.PutI.bias,
e2));
break;
- case Ist_Tmp:
- if (isFlat(st->Ist.Tmp.data)) {
+ case Ist_WrTmp:
+ if (isFlat(st->Ist.WrTmp.data)) {
/* optimisation, to reduce the number of tmp-tmp
copies generated */
- addStmtToIRBB(bb, st);
+ addStmtToIRSB(bb, st);
} else {
/* general case, always correct */
- e1 = flatten_Expr(bb, st->Ist.Tmp.data);
- addStmtToIRBB(bb, IRStmt_Tmp(st->Ist.Tmp.tmp, e1));
+ e1 = flatten_Expr(bb, st->Ist.WrTmp.data);
+ addStmtToIRSB(bb, IRStmt_WrTmp(st->Ist.WrTmp.tmp, e1));
}
break;
case Ist_Store:
e1 = flatten_Expr(bb, st->Ist.Store.addr);
e2 = flatten_Expr(bb, st->Ist.Store.data);
- addStmtToIRBB(bb, IRStmt_Store(st->Ist.Store.end, e1,e2));
+ addStmtToIRSB(bb, IRStmt_Store(st->Ist.Store.end, e1,e2));
break;
case Ist_Dirty:
d = st->Ist.Dirty.details;
d2 = emptyIRDirty();
*d2 = *d;
- d2->args = sopyIRExprVec(d2->args);
+ d2->args = shallowCopyIRExprVec(d2->args);
if (d2->mFx != Ifx_None) {
d2->mAddr = flatten_Expr(bb, d2->mAddr);
} else {
d2->guard = flatten_Expr(bb, d2->guard);
for (i = 0; d2->args[i]; i++)
d2->args[i] = flatten_Expr(bb, d2->args[i]);
- addStmtToIRBB(bb, IRStmt_Dirty(d2));
+ addStmtToIRSB(bb, IRStmt_Dirty(d2));
break;
case Ist_NoOp:
case Ist_MFence:
case Ist_IMark:
- addStmtToIRBB(bb, st);
+ addStmtToIRSB(bb, st);
break;
case Ist_AbiHint:
e1 = flatten_Expr(bb, st->Ist.AbiHint.base);
- addStmtToIRBB(bb, IRStmt_AbiHint(e1, st->Ist.AbiHint.len));
+ addStmtToIRSB(bb, IRStmt_AbiHint(e1, st->Ist.AbiHint.len));
break;
case Ist_Exit:
e1 = flatten_Expr(bb, st->Ist.Exit.guard);
- addStmtToIRBB(bb, IRStmt_Exit(e1, st->Ist.Exit.jk,
+ addStmtToIRSB(bb, IRStmt_Exit(e1, st->Ist.Exit.jk,
st->Ist.Exit.dst));
break;
default:
}
-static IRBB* flatten_BB ( IRBB* in )
+static IRSB* flatten_BB ( IRSB* in )
{
Int i;
- IRBB* out;
- out = emptyIRBB();
- out->tyenv = dopyIRTypeEnv( in->tyenv );
+ IRSB* out;
+ out = emptyIRSB();
+ out->tyenv = deepCopyIRTypeEnv( in->tyenv );
for (i = 0; i < in->stmts_used; i++)
if (in->stmts[i])
flatten_Stmt( out, in->stmts[i] );
/* Extract the min/max offsets from a guest state array descriptor. */
inline
-static void getArrayBounds ( IRArray* descr, UInt* minoff, UInt* maxoff )
+static void getArrayBounds ( IRRegArray* descr,
+ UInt* minoff, UInt* maxoff )
{
*minoff = descr->base;
*maxoff = *minoff + descr->nElems*sizeofIRType(descr->elemTy) - 1;
return (minoff << 16) | maxoff;
}
-static UInt mk_key_GetIPutI ( IRArray* descr )
+static UInt mk_key_GetIPutI ( IRRegArray* descr )
{
UInt minoff, maxoff;
getArrayBounds( descr, &minoff, &maxoff );
}
-static void redundant_get_removal_BB ( IRBB* bb )
+static void redundant_get_removal_BB ( IRSB* bb )
{
HashHW* env = newHHW();
UInt key = 0; /* keep gcc -O happy */
continue;
/* Deal with Gets */
- if (st->tag == Ist_Tmp
- && st->Ist.Tmp.data->tag == Iex_Get) {
+ if (st->tag == Ist_WrTmp
+ && st->Ist.WrTmp.data->tag == Iex_Get) {
/* st is 't = Get(...)'. Look up in the environment and see
if the Get can be replaced. */
- IRExpr* get = st->Ist.Tmp.data;
+ IRExpr* get = st->Ist.WrTmp.data;
key = (HWord)mk_key_GetPut( get->Iex.Get.offset,
get->Iex.Get.ty );
if (lookupHHW(env, &val, (HWord)key)) {
would make maintaining flatness more difficult. */
IRExpr* valE = (IRExpr*)val;
Bool typesOK = toBool( typeOfIRExpr(bb->tyenv,valE)
- == st->Ist.Tmp.data->Iex.Get.ty );
+ == st->Ist.WrTmp.data->Iex.Get.ty );
if (typesOK && DEBUG_IROPT) {
vex_printf("rGET: "); ppIRExpr(get);
vex_printf(" -> "); ppIRExpr(valE);
vex_printf("\n");
}
if (typesOK)
- bb->stmts[i] = IRStmt_Tmp(st->Ist.Tmp.tmp, valE);
+ bb->stmts[i] = IRStmt_WrTmp(st->Ist.WrTmp.tmp, valE);
} else {
/* Not found, but at least we know that t and the Get(...)
are now associated. So add a binding to reflect that
fact. */
addToHHW( env, (HWord)key,
- (HWord)(void*)(IRExpr_Tmp(st->Ist.Tmp.tmp)) );
+ (HWord)(void*)(IRExpr_RdTmp(st->Ist.WrTmp.tmp)) );
}
}
/* Find any Get uses in st and invalidate any partially or fully
overlapping ranges listed in env. Due to the flattening phase, the
- only stmt kind we expect to find a Get on is IRStmt_Tmp. */
+ only stmt kind we expect to find a Get on is IRStmt_WrTmp. */
static void handle_gets_Stmt (
HashHW* env,
/* This is the only interesting case. Deal with Gets in the RHS
expression. */
- case Ist_Tmp:
- e = st->Ist.Tmp.data;
+ case Ist_WrTmp:
+ e = st->Ist.WrTmp.data;
switch (e->tag) {
case Iex_Get:
isGet = True;
*/
static void redundant_put_removal_BB (
- IRBB* bb,
+ IRSB* bb,
Bool (*preciseMemExnsFn)(Int,Int)
)
{
/* Are both expressions simply the same IRTemp ? */
static Bool sameIRTemps ( IRExpr* e1, IRExpr* e2 )
{
- return toBool( e1->tag == Iex_Tmp
- && e2->tag == Iex_Tmp
- && e1->Iex.Tmp.tmp == e2->Iex.Tmp.tmp );
+ return toBool( e1->tag == Iex_RdTmp
+ && e2->tag == Iex_RdTmp
+ && e1->Iex.RdTmp.tmp == e2->Iex.RdTmp.tmp );
}
static Bool notBool ( Bool b )
simplest just to get rid of the problem by rewriting it
out, since the opportunity to do so exists. */
if (e->Iex.Binop.op == Iop_Add32
- && e->Iex.Binop.arg1->tag == Iex_Tmp
- && e->Iex.Binop.arg2->tag == Iex_Tmp
- && e->Iex.Binop.arg1->Iex.Tmp.tmp
- == e->Iex.Binop.arg2->Iex.Tmp.tmp) {
+ && e->Iex.Binop.arg1->tag == Iex_RdTmp
+ && e->Iex.Binop.arg2->tag == Iex_RdTmp
+ && e->Iex.Binop.arg1->Iex.RdTmp.tmp
+ == e->Iex.Binop.arg2->Iex.RdTmp.tmp) {
e2 = IRExpr_Binop(Iop_Shl32,
e->Iex.Binop.arg1,
IRExpr_Const(IRConst_U8(1)));
/* Add64(t,t) ==> t << 1; rationale as for Add32(t,t) above. */
if (e->Iex.Binop.op == Iop_Add64
- && e->Iex.Binop.arg1->tag == Iex_Tmp
- && e->Iex.Binop.arg2->tag == Iex_Tmp
- && e->Iex.Binop.arg1->Iex.Tmp.tmp
- == e->Iex.Binop.arg2->Iex.Tmp.tmp) {
+ && e->Iex.Binop.arg1->tag == Iex_RdTmp
+ && e->Iex.Binop.arg2->tag == Iex_RdTmp
+ && e->Iex.Binop.arg1->Iex.RdTmp.tmp
+ == e->Iex.Binop.arg2->Iex.RdTmp.tmp) {
e2 = IRExpr_Binop(Iop_Shl64,
e->Iex.Binop.arg1,
IRExpr_Const(IRConst_U8(1)));
static IRExpr* subst_Expr ( IRExpr** env, IRExpr* ex )
{
switch (ex->tag) {
- case Iex_Tmp:
- if (env[(Int)ex->Iex.Tmp.tmp] != NULL) {
- return env[(Int)ex->Iex.Tmp.tmp];
+ case Iex_RdTmp:
+ if (env[(Int)ex->Iex.RdTmp.tmp] != NULL) {
+ return env[(Int)ex->Iex.RdTmp.tmp];
} else {
/* not bound in env */
return ex;
case Iex_CCall: {
Int i;
- IRExpr** args2 = sopyIRExprVec(ex->Iex.CCall.args);
+ IRExpr** args2 = shallowCopyIRExprVec(ex->Iex.CCall.args);
for (i = 0; args2[i]; i++) {
vassert(isIRAtom(args2[i]));
args2[i] = subst_Expr(env, args2[i]);
fold_Expr(subst_Expr(env, st->Ist.PutI.data))
);
- case Ist_Tmp:
- /* This is the one place where an expr (st->Ist.Tmp.data) is
+ case Ist_WrTmp:
+ /* This is the one place where an expr (st->Ist.WrTmp.data) is
allowed to be more than just a constant or a tmp. */
- return IRStmt_Tmp(
- st->Ist.Tmp.tmp,
- fold_Expr(subst_Expr(env, st->Ist.Tmp.data))
+ return IRStmt_WrTmp(
+ st->Ist.WrTmp.tmp,
+ fold_Expr(subst_Expr(env, st->Ist.WrTmp.data))
);
case Ist_Store:
d = st->Ist.Dirty.details;
d2 = emptyIRDirty();
*d2 = *d;
- d2->args = sopyIRExprVec(d2->args);
+ d2->args = shallowCopyIRExprVec(d2->args);
if (d2->mFx != Ifx_None) {
vassert(isIRAtom(d2->mAddr));
d2->mAddr = fold_Expr(subst_Expr(env, d2->mAddr));
}
-IRBB* cprop_BB ( IRBB* in )
+IRSB* cprop_BB ( IRSB* in )
{
Int i;
- IRBB* out;
+ IRSB* out;
IRStmt* st2;
Int n_tmps = in->tyenv->types_used;
IRExpr** env = LibVEX_Alloc(n_tmps * sizeof(IRExpr*));
- out = emptyIRBB();
- out->tyenv = dopyIRTypeEnv( in->tyenv );
+ out = emptyIRSB();
+ out->tyenv = deepCopyIRTypeEnv( in->tyenv );
/* Set up the env with which travels forward. This holds a
substitution, mapping IRTemps to atoms, that is, IRExprs which
F64i, so that F64i literals can be CSE'd later. This helps
x86 floating point code generation. */
- if (st2->tag == Ist_Tmp
- && st2->Ist.Tmp.data->tag == Iex_Const
- && st2->Ist.Tmp.data->Iex.Const.con->tag != Ico_F64i) {
+ if (st2->tag == Ist_WrTmp
+ && st2->Ist.WrTmp.data->tag == Iex_Const
+ && st2->Ist.WrTmp.data->Iex.Const.con->tag != Ico_F64i) {
/* 't = const' -- add to env.
The pair (IRTemp, IRExpr*) is added. */
- env[(Int)(st2->Ist.Tmp.tmp)] = st2->Ist.Tmp.data;
+ env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
}
else
- if (st2->tag == Ist_Tmp && st2->Ist.Tmp.data->tag == Iex_Tmp) {
+ if (st2->tag == Ist_WrTmp && st2->Ist.WrTmp.data->tag == Iex_RdTmp) {
/* 't1 = t2' -- add to env.
The pair (IRTemp, IRExpr*) is added. */
- env[(Int)(st2->Ist.Tmp.tmp)] = st2->Ist.Tmp.data;
+ env[(Int)(st2->Ist.WrTmp.tmp)] = st2->Ist.WrTmp.data;
}
else {
/* Not interesting, copy st2 into the output block. */
- addStmtToIRBB( out, st2 );
+ addStmtToIRSB( out, st2 );
}
}
case Iex_Unop:
addUses_Expr(set, e->Iex.Unop.arg);
return;
- case Iex_Tmp:
- addUses_Temp(set, e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ addUses_Temp(set, e->Iex.RdTmp.tmp);
return;
case Iex_Const:
case Iex_Get:
addUses_Expr(set, st->Ist.PutI.ix);
addUses_Expr(set, st->Ist.PutI.data);
return;
- case Ist_Tmp:
- addUses_Expr(set, st->Ist.Tmp.data);
+ case Ist_WrTmp:
+ addUses_Expr(set, st->Ist.WrTmp.data);
return;
case Ist_Put:
addUses_Expr(set, st->Ist.Put.data);
}
-/* Note, this destructively modifies the given IRBB. */
+/* Note, this destructively modifies the given IRSB. */
/* Scan backwards through statements, carrying a set of IRTemps which
are known to be used after the current point. On encountering 't =
all statements following it are turned into no-ops.
*/
-/* notstatic */ void do_deadcode_BB ( IRBB* bb )
+/* notstatic */ void do_deadcode_BB ( IRSB* bb )
{
Int i, i_unconditional_exit;
Int n_tmps = bb->tyenv->types_used;
if (st->tag == Ist_Exit
&& isOneU1(st->Ist.Exit.guard))
i_unconditional_exit = i;
- if (st->tag == Ist_Tmp
- && set[(Int)(st->Ist.Tmp.tmp)] == False) {
+ if (st->tag == Ist_WrTmp
+ && set[(Int)(st->Ist.WrTmp.tmp)] == False) {
/* it's an IRTemp which never got used. Delete it. */
if (DEBUG_IROPT) {
vex_printf("DEAD: ");
/*---------------------------------------------------------------*/
static
-IRBB* spec_helpers_BB ( IRBB* bb,
+IRSB* spec_helpers_BB ( IRSB* bb,
IRExpr* (*specHelper) ( HChar*, IRExpr**) )
{
Int i;
for (i = bb->stmts_used-1; i >= 0; i--) {
st = bb->stmts[i];
- if (st->tag != Ist_Tmp
- || st->Ist.Tmp.data->tag != Iex_CCall)
+ if (st->tag != Ist_WrTmp
+ || st->Ist.WrTmp.data->tag != Iex_CCall)
continue;
- ex = (*specHelper)( st->Ist.Tmp.data->Iex.CCall.cee->name,
- st->Ist.Tmp.data->Iex.CCall.args );
+ ex = (*specHelper)( st->Ist.WrTmp.data->Iex.CCall.cee->name,
+ st->Ist.WrTmp.data->Iex.CCall.args );
if (!ex)
/* the front end can't think of a suitable replacement */
continue;
/* We got something better. Install it in the bb. */
any = True;
bb->stmts[i]
- = IRStmt_Tmp(st->Ist.Tmp.tmp, ex);
+ = IRStmt_WrTmp(st->Ist.WrTmp.tmp, ex);
if (0) {
vex_printf("SPEC: ");
- ppIRExpr(st->Ist.Tmp.data);
+ ppIRExpr(st->Ist.WrTmp.data);
vex_printf(" --> ");
ppIRExpr(ex);
vex_printf("\n");
state access and a non-indexed access. */
static
-GSAliasing getAliasingRelation_IC ( IRArray* descr1, IRExpr* ix1,
+GSAliasing getAliasingRelation_IC ( IRRegArray* descr1, IRExpr* ix1,
Int offset2, IRType ty2 )
{
UInt minoff1, maxoff1, minoff2, maxoff2;
static
GSAliasing getAliasingRelation_II (
- IRArray* descr1, IRExpr* ix1, Int bias1,
- IRArray* descr2, IRExpr* ix2, Int bias2
+ IRRegArray* descr1, IRExpr* ix1, Int bias1,
+ IRRegArray* descr2, IRExpr* ix2, Int bias2
)
{
UInt minoff1, maxoff1, minoff2, maxoff2;
/* So the two arrays at least partially overlap. To get any
further we'll have to be sure that the descriptors are
identical. */
- if (!eqIRArray(descr1, descr2))
+ if (!eqIRRegArray(descr1, descr2))
return UnknownAlias;
/* The descriptors are identical. Now the only difference can be
} Mttt;
/* GetI(descr,tmp,bias)*/
struct {
- IRArray* descr;
- IRTemp ix;
- Int bias;
+ IRRegArray* descr;
+ IRTemp ix;
+ Int bias;
} GetIt;
} u;
}
&& a1->u.Mttt.e0 == a2->u.Mttt.e0
&& a1->u.Mttt.eX == a2->u.Mttt.eX);
case GetIt:
- return toBool(eqIRArray(a1->u.GetIt.descr, a2->u.GetIt.descr)
+ return toBool(eqIRRegArray(a1->u.GetIt.descr, a2->u.GetIt.descr)
&& a1->u.GetIt.ix == a2->u.GetIt.ix
&& a1->u.GetIt.bias == a2->u.GetIt.bias);
default: vpanic("eq_AvailExpr");
IRConst* con;
switch (ae->tag) {
case Ut:
- return IRExpr_Unop( ae->u.Ut.op, IRExpr_Tmp(ae->u.Ut.arg) );
+ return IRExpr_Unop( ae->u.Ut.op, IRExpr_RdTmp(ae->u.Ut.arg) );
case Btt:
return IRExpr_Binop( ae->u.Btt.op,
- IRExpr_Tmp(ae->u.Btt.arg1),
- IRExpr_Tmp(ae->u.Btt.arg2) );
+ IRExpr_RdTmp(ae->u.Btt.arg1),
+ IRExpr_RdTmp(ae->u.Btt.arg2) );
case Btc:
con = LibVEX_Alloc(sizeof(IRConst));
*con = ae->u.Btc.con2;
return IRExpr_Binop( ae->u.Btc.op,
- IRExpr_Tmp(ae->u.Btc.arg1), IRExpr_Const(con) );
+ IRExpr_RdTmp(ae->u.Btc.arg1),
+ IRExpr_Const(con) );
case Bct:
con = LibVEX_Alloc(sizeof(IRConst));
*con = ae->u.Bct.con1;
return IRExpr_Binop( ae->u.Bct.op,
- IRExpr_Const(con), IRExpr_Tmp(ae->u.Bct.arg2) );
+ IRExpr_Const(con),
+ IRExpr_RdTmp(ae->u.Bct.arg2) );
case Cf64i:
return IRExpr_Const(IRConst_F64i(ae->u.Cf64i.f64i));
case Mttt:
- return IRExpr_Mux0X(IRExpr_Tmp(ae->u.Mttt.co),
- IRExpr_Tmp(ae->u.Mttt.e0),
- IRExpr_Tmp(ae->u.Mttt.eX));
+ return IRExpr_Mux0X(IRExpr_RdTmp(ae->u.Mttt.co),
+ IRExpr_RdTmp(ae->u.Mttt.e0),
+ IRExpr_RdTmp(ae->u.Mttt.eX));
case GetIt:
return IRExpr_GetI(ae->u.GetIt.descr,
- IRExpr_Tmp(ae->u.GetIt.ix),
+ IRExpr_RdTmp(ae->u.GetIt.ix),
ae->u.GetIt.bias);
default:
vpanic("availExpr_to_IRExpr");
AvailExpr* ae;
if (e->tag == Iex_Unop
- && e->Iex.Unop.arg->tag == Iex_Tmp) {
+ && e->Iex.Unop.arg->tag == Iex_RdTmp) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = Ut;
ae->u.Ut.op = e->Iex.Unop.op;
- ae->u.Ut.arg = e->Iex.Unop.arg->Iex.Tmp.tmp;
+ ae->u.Ut.arg = e->Iex.Unop.arg->Iex.RdTmp.tmp;
return ae;
}
if (e->tag == Iex_Binop
- && e->Iex.Binop.arg1->tag == Iex_Tmp
- && e->Iex.Binop.arg2->tag == Iex_Tmp) {
+ && e->Iex.Binop.arg1->tag == Iex_RdTmp
+ && e->Iex.Binop.arg2->tag == Iex_RdTmp) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = Btt;
ae->u.Btt.op = e->Iex.Binop.op;
- ae->u.Btt.arg1 = e->Iex.Binop.arg1->Iex.Tmp.tmp;
- ae->u.Btt.arg2 = e->Iex.Binop.arg2->Iex.Tmp.tmp;
+ ae->u.Btt.arg1 = e->Iex.Binop.arg1->Iex.RdTmp.tmp;
+ ae->u.Btt.arg2 = e->Iex.Binop.arg2->Iex.RdTmp.tmp;
return ae;
}
if (e->tag == Iex_Binop
- && e->Iex.Binop.arg1->tag == Iex_Tmp
+ && e->Iex.Binop.arg1->tag == Iex_RdTmp
&& e->Iex.Binop.arg2->tag == Iex_Const) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = Btc;
ae->u.Btc.op = e->Iex.Binop.op;
- ae->u.Btc.arg1 = e->Iex.Binop.arg1->Iex.Tmp.tmp;
+ ae->u.Btc.arg1 = e->Iex.Binop.arg1->Iex.RdTmp.tmp;
ae->u.Btc.con2 = *(e->Iex.Binop.arg2->Iex.Const.con);
return ae;
}
if (e->tag == Iex_Binop
&& e->Iex.Binop.arg1->tag == Iex_Const
- && e->Iex.Binop.arg2->tag == Iex_Tmp) {
+ && e->Iex.Binop.arg2->tag == Iex_RdTmp) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = Bct;
ae->u.Bct.op = e->Iex.Binop.op;
- ae->u.Bct.arg2 = e->Iex.Binop.arg2->Iex.Tmp.tmp;
+ ae->u.Bct.arg2 = e->Iex.Binop.arg2->Iex.RdTmp.tmp;
ae->u.Bct.con1 = *(e->Iex.Binop.arg1->Iex.Const.con);
return ae;
}
}
if (e->tag == Iex_Mux0X
- && e->Iex.Mux0X.cond->tag == Iex_Tmp
- && e->Iex.Mux0X.expr0->tag == Iex_Tmp
- && e->Iex.Mux0X.exprX->tag == Iex_Tmp) {
+ && e->Iex.Mux0X.cond->tag == Iex_RdTmp
+ && e->Iex.Mux0X.expr0->tag == Iex_RdTmp
+ && e->Iex.Mux0X.exprX->tag == Iex_RdTmp) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = Mttt;
- ae->u.Mttt.co = e->Iex.Mux0X.cond->Iex.Tmp.tmp;
- ae->u.Mttt.e0 = e->Iex.Mux0X.expr0->Iex.Tmp.tmp;
- ae->u.Mttt.eX = e->Iex.Mux0X.exprX->Iex.Tmp.tmp;
+ ae->u.Mttt.co = e->Iex.Mux0X.cond->Iex.RdTmp.tmp;
+ ae->u.Mttt.e0 = e->Iex.Mux0X.expr0->Iex.RdTmp.tmp;
+ ae->u.Mttt.eX = e->Iex.Mux0X.exprX->Iex.RdTmp.tmp;
return ae;
}
if (e->tag == Iex_GetI
- && e->Iex.GetI.ix->tag == Iex_Tmp) {
+ && e->Iex.GetI.ix->tag == Iex_RdTmp) {
ae = LibVEX_Alloc(sizeof(AvailExpr));
ae->tag = GetIt;
ae->u.GetIt.descr = e->Iex.GetI.descr;
- ae->u.GetIt.ix = e->Iex.GetI.ix->Iex.Tmp.tmp;
+ ae->u.GetIt.ix = e->Iex.GetI.ix->Iex.RdTmp.tmp;
ae->u.GetIt.bias = e->Iex.GetI.bias;
return ae;
}
/* The BB is modified in-place. Returns True if any changes were
made. */
-static Bool do_cse_BB ( IRBB* bb )
+static Bool do_cse_BB ( IRSB* bb )
{
Int i, j, paranoia;
IRTemp t, q;
vassert(sizeof(IRTemp) <= sizeof(HWord));
- if (0) { ppIRBB(bb); vex_printf("\n\n"); }
+ if (0) { ppIRSB(bb); vex_printf("\n\n"); }
/* Iterate forwards over the stmts.
On seeing "t = E", where E is one of the 5 AvailExpr forms:
case Ist_Put: case Ist_PutI:
paranoia = 1; break;
case Ist_NoOp: case Ist_IMark: case Ist_AbiHint:
- case Ist_Tmp: case Ist_MFence: case Ist_Exit:
+ case Ist_WrTmp: case Ist_MFence: case Ist_Exit:
paranoia = 0; break;
default:
vpanic("do_cse_BB(1)");
if (st->tag == Ist_Put) {
if (getAliasingRelation_IC(
ae->u.GetIt.descr,
- IRExpr_Tmp(ae->u.GetIt.ix),
+ IRExpr_RdTmp(ae->u.GetIt.ix),
st->Ist.Put.offset,
typeOfIRExpr(bb->tyenv,st->Ist.Put.data)
) != NoAlias)
if (st->tag == Ist_PutI) {
if (getAliasingRelation_II(
ae->u.GetIt.descr,
- IRExpr_Tmp(ae->u.GetIt.ix),
+ IRExpr_RdTmp(ae->u.GetIt.ix),
ae->u.GetIt.bias,
st->Ist.PutI.descr,
st->Ist.PutI.ix,
/* ------ ENV invalidate aenv bindings ------ */
/* ignore not-interestings */
- if (st->tag != Ist_Tmp)
+ if (st->tag != Ist_WrTmp)
continue;
- t = st->Ist.Tmp.tmp;
- eprime = irExpr_to_AvailExpr(st->Ist.Tmp.data);
+ t = st->Ist.WrTmp.tmp;
+ eprime = irExpr_to_AvailExpr(st->Ist.WrTmp.data);
/* ignore if not of AvailExpr form */
if (!eprime)
continue;
note the t->q binding in tenv. */
/* (this is the core of the CSE action) */
q = (IRTemp)aenv->val[j];
- bb->stmts[i] = IRStmt_Tmp( t, IRExpr_Tmp(q) );
+ bb->stmts[i] = IRStmt_WrTmp( t, IRExpr_RdTmp(q) );
addToHHW( tenv, (HWord)t, (HWord)q );
anyDone = True;
} else {
/* No binding was found, so instead we add E' -> t to our
collection of available expressions, replace this stmt
with "t = E'", and move on. */
- bb->stmts[i] = IRStmt_Tmp( t, availExpr_to_IRExpr(eprime) );
+ bb->stmts[i] = IRStmt_WrTmp( t, availExpr_to_IRExpr(eprime) );
addToHHW( aenv, (HWord)eprime, (HWord)t );
}
}
/*
- ppIRBB(bb);
- sanityCheckIRBB(bb, Ity_I32);
+ ppIRSB(bb);
+ sanityCheckIRSB(bb, Ity_I32);
vex_printf("\n\n");
*/
return anyDone;
return False;
if (e->Iex.Binop.op != Iop_Add32 && e->Iex.Binop.op != Iop_Sub32)
return False;
- if (e->Iex.Binop.arg1->tag != Iex_Tmp)
+ if (e->Iex.Binop.arg1->tag != Iex_RdTmp)
return False;
if (e->Iex.Binop.arg2->tag != Iex_Const)
return False;
- *tmp = e->Iex.Binop.arg1->Iex.Tmp.tmp;
+ *tmp = e->Iex.Binop.arg1->Iex.RdTmp.tmp;
*i32 = (Int)(e->Iex.Binop.arg2->Iex.Const.con->Ico.U32);
if (e->Iex.Binop.op == Iop_Sub32)
*i32 = -*i32;
other tmp2. Scan backwards from the specified start point -- an
optimisation. */
-static Bool collapseChain ( IRBB* bb, Int startHere,
+static Bool collapseChain ( IRSB* bb, Int startHere,
IRTemp tmp,
IRTemp* tmp2, Int* i32 )
{
+/- a constant. */
for (j = startHere; j >= 0; j--) {
st = bb->stmts[j];
- if (st->tag != Ist_Tmp)
+ if (st->tag != Ist_WrTmp)
continue;
- if (st->Ist.Tmp.tmp != var)
+ if (st->Ist.WrTmp.tmp != var)
continue;
- e = st->Ist.Tmp.data;
+ e = st->Ist.WrTmp.data;
if (!isAdd32OrSub32(e, &vv, &ii))
break;
var = vv;
/* ------- Main function for Add32/Sub32 chain collapsing ------ */
-static void collapse_AddSub_chains_BB ( IRBB* bb )
+static void collapse_AddSub_chains_BB ( IRSB* bb )
{
IRStmt *st;
IRTemp var, var2;
/* Try to collapse 't1 = Add32/Sub32(t2, con)'. */
- if (st->tag == Ist_Tmp
- && isAdd32OrSub32(st->Ist.Tmp.data, &var, &con)) {
+ if (st->tag == Ist_WrTmp
+ && isAdd32OrSub32(st->Ist.WrTmp.data, &var, &con)) {
/* So e1 is of the form Add32(var,con) or Sub32(var,-con).
Find out if var can be expressed as var2 + con2. */
}
con2 += con;
bb->stmts[i]
- = IRStmt_Tmp(
- st->Ist.Tmp.tmp,
+ = IRStmt_WrTmp(
+ st->Ist.WrTmp.tmp,
(con2 >= 0)
? IRExpr_Binop(Iop_Add32,
- IRExpr_Tmp(var2),
+ IRExpr_RdTmp(var2),
IRExpr_Const(IRConst_U32(con2)))
: IRExpr_Binop(Iop_Sub32,
- IRExpr_Tmp(var2),
+ IRExpr_RdTmp(var2),
IRExpr_Const(IRConst_U32(-con2)))
);
if (DEBUG_IROPT) {
/* Try to collapse 't1 = GetI[t2, con]'. */
- if (st->tag == Ist_Tmp
- && st->Ist.Tmp.data->tag == Iex_GetI
- && st->Ist.Tmp.data->Iex.GetI.ix->tag == Iex_Tmp
- && collapseChain(bb, i-1, st->Ist.Tmp.data->Iex.GetI.ix
- ->Iex.Tmp.tmp, &var2, &con2)) {
+ if (st->tag == Ist_WrTmp
+ && st->Ist.WrTmp.data->tag == Iex_GetI
+ && st->Ist.WrTmp.data->Iex.GetI.ix->tag == Iex_RdTmp
+ && collapseChain(bb, i-1, st->Ist.WrTmp.data->Iex.GetI.ix
+ ->Iex.RdTmp.tmp, &var2, &con2)) {
if (DEBUG_IROPT) {
vex_printf("replacing3 ");
ppIRStmt(st);
vex_printf(" with ");
}
- con2 += st->Ist.Tmp.data->Iex.GetI.bias;
+ con2 += st->Ist.WrTmp.data->Iex.GetI.bias;
bb->stmts[i]
- = IRStmt_Tmp(
- st->Ist.Tmp.tmp,
- IRExpr_GetI(st->Ist.Tmp.data->Iex.GetI.descr,
- IRExpr_Tmp(var2),
+ = IRStmt_WrTmp(
+ st->Ist.WrTmp.tmp,
+ IRExpr_GetI(st->Ist.WrTmp.data->Iex.GetI.descr,
+ IRExpr_RdTmp(var2),
con2));
if (DEBUG_IROPT) {
ppIRStmt(bb->stmts[i]);
/* Perhaps st is PutI[t, con] ? */
if (st->tag == Ist_PutI
- && st->Ist.PutI.ix->tag == Iex_Tmp
- && collapseChain(bb, i-1, st->Ist.PutI.ix->Iex.Tmp.tmp,
+ && st->Ist.PutI.ix->tag == Iex_RdTmp
+ && collapseChain(bb, i-1, st->Ist.PutI.ix->Iex.RdTmp.tmp,
&var2, &con2)) {
if (DEBUG_IROPT) {
vex_printf("replacing2 ");
con2 += st->Ist.PutI.bias;
bb->stmts[i]
= IRStmt_PutI(st->Ist.PutI.descr,
- IRExpr_Tmp(var2),
+ IRExpr_RdTmp(var2),
con2,
st->Ist.PutI.data);
if (DEBUG_IROPT) {
that the PutI writes. This is the core of PutI-GetI forwarding. */
static
-IRExpr* findPutI ( IRBB* bb, Int startHere,
- IRArray* descrG, IRExpr* ixG, Int biasG )
+IRExpr* findPutI ( IRSB* bb, Int startHere,
+ IRRegArray* descrG, IRExpr* ixG, Int biasG )
{
Int j;
IRStmt* st;
if (0) {
vex_printf("\nfindPutI ");
- ppIRArray(descrG);
+ ppIRRegArray(descrG);
vex_printf(" ");
ppIRExpr(ixG);
vex_printf(" %d\n", biasG);
);
goto have_relation;
- case Ist_Tmp:
- if (s2->Ist.Tmp.data->tag == Iex_GetI) {
+ case Ist_WrTmp:
+ if (s2->Ist.WrTmp.data->tag == Iex_GetI) {
relation
= getAliasingRelation_II(
pi->Ist.PutI.descr, pi->Ist.PutI.ix,
pi->Ist.PutI.bias,
- s2->Ist.Tmp.data->Iex.GetI.descr,
- s2->Ist.Tmp.data->Iex.GetI.ix,
- s2->Ist.Tmp.data->Iex.GetI.bias
+ s2->Ist.WrTmp.data->Iex.GetI.descr,
+ s2->Ist.WrTmp.data->Iex.GetI.ix,
+ s2->Ist.WrTmp.data->Iex.GetI.bias
);
goto have_relation;
}
- if (s2->Ist.Tmp.data->tag == Iex_Get) {
+ if (s2->Ist.WrTmp.data->tag == Iex_Get) {
relation
= getAliasingRelation_IC(
pi->Ist.PutI.descr, pi->Ist.PutI.ix,
- s2->Ist.Tmp.data->Iex.Get.offset,
- s2->Ist.Tmp.data->Iex.Get.ty
+ s2->Ist.WrTmp.data->Iex.Get.offset,
+ s2->Ist.WrTmp.data->Iex.Get.ty
);
goto have_relation;
}
bb is modified in-place. */
static
-void do_redundant_GetI_elimination ( IRBB* bb )
+void do_redundant_GetI_elimination ( IRSB* bb )
{
Int i;
IRStmt* st;
if (st->tag == Ist_NoOp)
continue;
- if (st->tag == Ist_Tmp
- && st->Ist.Tmp.data->tag == Iex_GetI
- && st->Ist.Tmp.data->Iex.GetI.ix->tag == Iex_Tmp) {
- IRArray* descr = st->Ist.Tmp.data->Iex.GetI.descr;
- IRExpr* ix = st->Ist.Tmp.data->Iex.GetI.ix;
- Int bias = st->Ist.Tmp.data->Iex.GetI.bias;
- IRExpr* replacement = findPutI(bb, i-1, descr, ix, bias);
+ if (st->tag == Ist_WrTmp
+ && st->Ist.WrTmp.data->tag == Iex_GetI
+ && st->Ist.WrTmp.data->Iex.GetI.ix->tag == Iex_RdTmp) {
+ IRRegArray* descr = st->Ist.WrTmp.data->Iex.GetI.descr;
+ IRExpr* ix = st->Ist.WrTmp.data->Iex.GetI.ix;
+ Int bias = st->Ist.WrTmp.data->Iex.GetI.bias;
+ IRExpr* replacement = findPutI(bb, i-1, descr, ix, bias);
if (replacement
&& isIRAtom(replacement)
/* Make sure we're doing a type-safe transformation! */
&& typeOfIRExpr(bb->tyenv, replacement) == descr->elemTy) {
if (DEBUG_IROPT) {
vex_printf("rGI: ");
- ppIRExpr(st->Ist.Tmp.data);
+ ppIRExpr(st->Ist.WrTmp.data);
vex_printf(" -> ");
ppIRExpr(replacement);
vex_printf("\n");
}
- bb->stmts[i] = IRStmt_Tmp(st->Ist.Tmp.tmp, replacement);
+ bb->stmts[i] = IRStmt_WrTmp(st->Ist.WrTmp.tmp, replacement);
}
}
}
bb is modified in-place. */
static
-void do_redundant_PutI_elimination ( IRBB* bb )
+void do_redundant_PutI_elimination ( IRSB* bb )
{
Int i, j;
Bool delete;
{
Int i;
switch (e->tag) {
- case Iex_Tmp:
- e->Iex.Tmp.tmp += delta;
+ case Iex_RdTmp:
+ e->Iex.RdTmp.tmp += delta;
break;
case Iex_Get:
case Iex_Const:
deltaIRExpr(st->Ist.PutI.ix, delta);
deltaIRExpr(st->Ist.PutI.data, delta);
break;
- case Ist_Tmp:
- st->Ist.Tmp.tmp += delta;
- deltaIRExpr(st->Ist.Tmp.data, delta);
+ case Ist_WrTmp:
+ st->Ist.WrTmp.tmp += delta;
+ deltaIRExpr(st->Ist.WrTmp.data, delta);
break;
case Ist_Exit:
deltaIRExpr(st->Ist.Exit.guard, delta);
X and Y must be literal (guest) addresses.
*/
-static Int calc_unroll_factor( IRBB* bb )
+static Int calc_unroll_factor( IRSB* bb )
{
Int n_stmts, i;
}
-static IRBB* maybe_loop_unroll_BB ( IRBB* bb0, Addr64 my_addr )
+static IRSB* maybe_loop_unroll_BB ( IRSB* bb0, Addr64 my_addr )
{
Int i, j, jmax, n_vars;
Bool xxx_known;
IRExpr* udst;
IRStmt* st;
IRConst* con;
- IRBB *bb1, *bb2;
+ IRSB *bb1, *bb2;
Int unroll_factor;
if (vex_control.iropt_unroll_thresh <= 0)
unroll_factor = calc_unroll_factor( bb0 );
if (unroll_factor < 2)
return NULL;
- bb1 = dopyIRBB( bb0 );
+ bb1 = deepCopyIRSB( bb0 );
bb0 = NULL;
udst = NULL; /* is now invalid */
goto do_unroll;
if (unroll_factor < 2)
return NULL;
- bb1 = dopyIRBB( bb0 );
+ bb1 = deepCopyIRSB( bb0 );
bb0 = NULL;
udst = NULL; /* is now invalid */
for (i = bb1->stmts_used-1; i >= 0; i--)
/* negate the test condition */
st->Ist.Exit.guard
- = IRExpr_Unop(Iop_Not1,dopyIRExpr(st->Ist.Exit.guard));
+ = IRExpr_Unop(Iop_Not1,deepCopyIRExpr(st->Ist.Exit.guard));
/* --- The unroller proper. Both idioms are by now --- */
/* --- now converted to idiom 1. --- */
n_vars = bb1->tyenv->types_used;
- bb2 = dopyIRBB(bb1);
+ bb2 = deepCopyIRSB(bb1);
for (i = 0; i < n_vars; i++)
(void)newIRTemp(bb1->tyenv, bb2->tyenv->types[i]);
/* deltaIRStmt destructively modifies the stmt, but
that's OK since bb2 is a complete fresh copy of bb1. */
deltaIRStmt(bb2->stmts[i], n_vars);
- addStmtToIRBB(bb1, bb2->stmts[i]);
+ addStmtToIRSB(bb1, bb2->stmts[i]);
}
}
if (DEBUG_IROPT) {
vex_printf("\nUNROLLED (%llx)\n", my_addr);
- ppIRBB(bb1);
+ ppIRSB(bb1);
vex_printf("\n");
}
*doesGet = True;
setHints_Expr(doesLoad, doesGet, e->Iex.GetI.ix);
return;
- case Iex_Tmp:
+ case Iex_RdTmp:
case Iex_Const:
return;
default:
switch (e->tag) {
- case Iex_Tmp: /* the only interesting case */
- uses[e->Iex.Tmp.tmp]++;
+ case Iex_RdTmp: /* the only interesting case */
+ uses[e->Iex.RdTmp.tmp]++;
return;
case Iex_Mux0X:
case Ist_AbiHint:
aoccCount_Expr(uses, st->Ist.AbiHint.base);
return;
- case Ist_Tmp:
- aoccCount_Expr(uses, st->Ist.Tmp.data);
+ case Ist_WrTmp:
+ aoccCount_Expr(uses, st->Ist.WrTmp.data);
return;
case Ist_Put:
aoccCount_Expr(uses, st->Ist.Put.data);
switch (e->tag) {
case Iex_CCall:
- args2 = sopyIRExprVec(e->Iex.CCall.args);
+ args2 = shallowCopyIRExprVec(e->Iex.CCall.args);
for (i = 0; args2[i]; i++)
args2[i] = atbSubst_Expr(env,args2[i]);
return IRExpr_CCall(
e->Iex.CCall.retty,
args2
);
- case Iex_Tmp:
- e2 = atbSubst_Temp(env, e->Iex.Tmp.tmp);
+ case Iex_RdTmp:
+ e2 = atbSubst_Temp(env, e->Iex.RdTmp.tmp);
return e2 ? e2 : e;
case Iex_Mux0X:
return IRExpr_Mux0X(
atbSubst_Expr(env, st->Ist.Store.addr),
atbSubst_Expr(env, st->Ist.Store.data)
);
- case Ist_Tmp:
- return IRStmt_Tmp(
- st->Ist.Tmp.tmp,
- atbSubst_Expr(env, st->Ist.Tmp.data)
+ case Ist_WrTmp:
+ return IRStmt_WrTmp(
+ st->Ist.WrTmp.tmp,
+ atbSubst_Expr(env, st->Ist.WrTmp.data)
);
case Ist_Put:
return IRStmt_Put(
}
}
-/* notstatic */ void ado_treebuild_BB ( IRBB* bb )
+/* notstatic */ void ado_treebuild_BB ( IRSB* bb )
{
Int i, j, k, m;
Bool stmtPuts, stmtStores, invalidateMe;
/* Ensure there's at least one space in the env, by emitting
the oldest binding if necessary. */
if (env[A_NENV-1].bindee != NULL) {
- bb->stmts[j] = IRStmt_Tmp( env[A_NENV-1].binder, env[A_NENV-1].bindee );
+ bb->stmts[j] = IRStmt_WrTmp( env[A_NENV-1].binder,
+ env[A_NENV-1].bindee );
j++;
vassert(j <= i);
env[A_NENV-1].bindee = NULL;
}
/* Consider current stmt. */
- if (st->tag == Ist_Tmp && uses[st->Ist.Tmp.tmp] <= 1) {
+ if (st->tag == Ist_WrTmp && uses[st->Ist.WrTmp.tmp] <= 1) {
IRExpr *e, *e2;
/* optional extra: dump dead bindings as we find them.
Removes the need for a prior dead-code removal pass. */
- if (uses[st->Ist.Tmp.tmp] == 0) {
+ if (uses[st->Ist.WrTmp.tmp] == 0) {
if (0) vex_printf("DEAD binding\n");
continue; /* for (i = 0; i < bb->stmts_used; i++) loop */
}
- vassert(uses[st->Ist.Tmp.tmp] == 1);
+ vassert(uses[st->Ist.WrTmp.tmp] == 1);
/* ok, we have 't = E', occ(t)==1. Do the abovementioned
actions. */
- e = st->Ist.Tmp.data;
+ e = st->Ist.WrTmp.data;
e2 = atbSubst_Expr(env, e);
- addToEnvFront(env, st->Ist.Tmp.tmp, e2);
+ addToEnvFront(env, st->Ist.WrTmp.tmp, e2);
setHints_Expr(&env[0].doesLoad, &env[0].doesGet, e2);
/* don't advance j, as we are deleting this stmt and instead
holding it temporarily in the env. */
|| st->tag == Ist_AbiHint
);
if (invalidateMe) {
- bb->stmts[j] = IRStmt_Tmp( env[k].binder, env[k].bindee );
+ bb->stmts[j] = IRStmt_WrTmp( env[k].binder, env[k].bindee );
j++;
vassert(j <= i);
env[k].bindee = NULL;
static
-IRBB* cheap_transformations (
- IRBB* bb,
+IRSB* cheap_transformations (
+ IRSB* bb,
IRExpr* (*specHelper) (HChar*, IRExpr**),
Bool (*preciseMemExnsFn)(Int,Int)
)
redundant_get_removal_BB ( bb );
if (iropt_verbose) {
vex_printf("\n========= REDUNDANT GET\n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
redundant_put_removal_BB ( bb, preciseMemExnsFn );
if (iropt_verbose) {
vex_printf("\n========= REDUNDANT PUT\n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
bb = cprop_BB ( bb );
if (iropt_verbose) {
vex_printf("\n========= CPROPD\n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
do_deadcode_BB ( bb );
if (iropt_verbose) {
vex_printf("\n========= DEAD\n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
bb = spec_helpers_BB ( bb, specHelper );
do_deadcode_BB ( bb );
if (iropt_verbose) {
vex_printf("\n========= SPECd \n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
return bb;
optimising as much as possible in the presence of GetI and PutI. */
static
-IRBB* expensive_transformations( IRBB* bb )
+IRSB* expensive_transformations( IRSB* bb )
{
(void)do_cse_BB( bb );
collapse_AddSub_chains_BB( bb );
static void considerExpensives ( /*OUT*/Bool* hasGetIorPutI,
/*OUT*/Bool* hasVorFtemps,
- IRBB* bb )
+ IRSB* bb )
{
Int i, j;
IRStmt* st;
case Ist_PutI:
*hasGetIorPutI = True;
break;
- case Ist_Tmp:
- if (st->Ist.Tmp.data->tag == Iex_GetI)
+ case Ist_WrTmp:
+ if (st->Ist.WrTmp.data->tag == Iex_GetI)
*hasGetIorPutI = True;
- switch (typeOfIRTemp(bb->tyenv, st->Ist.Tmp.tmp)) {
+ switch (typeOfIRTemp(bb->tyenv, st->Ist.WrTmp.tmp)) {
case Ity_I1: case Ity_I8: case Ity_I16:
case Ity_I32: case Ity_I64: case Ity_I128:
break;
*/
-IRBB* do_iropt_BB ( IRBB* bb0,
+IRSB* do_iropt_BB ( IRSB* bb0,
IRExpr* (*specHelper) (HChar*, IRExpr**),
Bool (*preciseMemExnsFn)(Int,Int),
Addr64 guest_addr )
static Int n_expensive = 0;
Bool hasGetIorPutI, hasVorFtemps;
- IRBB *bb, *bb2;
+ IRSB *bb, *bb2;
n_total++;
if (iropt_verbose) {
vex_printf("\n========= FLAT\n\n" );
- ppIRBB(bb);
+ ppIRSB(bb);
}
/* If at level 0, stop now. */
/* Top level optimiser entry point. Returns a new BB. Operates
under the control of the global "vex_control" struct. */
extern
-IRBB* do_iropt_BB ( IRBB* bb,
+IRSB* do_iropt_BB ( IRSB* bb,
IRExpr* (*specHelper) (HChar*, IRExpr**),
Bool (*preciseMemExnsFn)(Int,Int),
Addr64 guest_addr );
/* Do a constant folding/propagation pass. */
extern
-IRBB* cprop_BB ( IRBB* );
+IRSB* cprop_BB ( IRSB* );
/* Do a dead-code removal pass. bb is destructively modified. */
extern
-void do_deadcode_BB ( IRBB* bb );
+void do_deadcode_BB ( IRSB* bb );
/* The tree-builder. Make (approximately) maximal safe trees. bb is
destructively modified. */
extern
-void ado_treebuild_BB ( IRBB* bb );
+void ado_treebuild_BB ( IRSB* bb );
#endif /* ndef __LIBVEX_IROPT_H */
HInstr* (*genReload) ( HReg, Int, Bool );
void (*ppInstr) ( HInstr*, Bool );
void (*ppReg) ( HReg );
- HInstrArray* (*iselBB) ( IRBB*, VexArch, VexArchInfo*,
- VexMiscInfo* );
+ HInstrArray* (*iselSB) ( IRSB*, VexArch, VexArchInfo*,
+ VexAbiInfo* );
Int (*emit) ( UChar*, Int, HInstr*, Bool, void* );
IRExpr* (*specHelper) ( HChar*, IRExpr** );
Bool (*preciseMemExnsFn) ( Int, Int );
VexGuestLayout* guest_layout;
Bool host_is_bigendian = False;
- IRBB* irbb;
+ IRSB* irsb;
HInstrArray* vcode;
HInstrArray* rcode;
Int i, j, k, out_used, guest_sizeB;
genReload = NULL;
ppInstr = NULL;
ppReg = NULL;
- iselBB = NULL;
+ iselSB = NULL;
emit = NULL;
specHelper = NULL;
preciseMemExnsFn = NULL;
genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86;
ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr;
ppReg = (void(*)(HReg)) ppHRegX86;
- iselBB = iselBB_X86;
+ iselSB = iselSB_X86;
emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_X86Instr;
host_is_bigendian = False;
host_word_type = Ity_I32;
genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64;
ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr;
ppReg = (void(*)(HReg)) ppHRegAMD64;
- iselBB = iselBB_AMD64;
+ iselSB = iselSB_AMD64;
emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_AMD64Instr;
host_is_bigendian = False;
host_word_type = Ity_I64;
genReload = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC;
ppInstr = (void(*)(HInstr*,Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
- iselBB = iselBB_PPC;
+ iselSB = iselSB_PPC;
emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr;
host_is_bigendian = True;
host_word_type = Ity_I32;
genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_PPC;
ppInstr = (void(*)(HInstr*, Bool)) ppPPCInstr;
ppReg = (void(*)(HReg)) ppHRegPPC;
- iselBB = iselBB_PPC;
+ iselSB = iselSB_PPC;
emit = (Int(*)(UChar*,Int,HInstr*,Bool,void*)) emit_PPCInstr;
host_is_bigendian = True;
host_word_type = Ity_I64;
" Front end "
"------------------------\n\n");
- irbb = bb_to_IR ( vta->guest_extents,
+ irsb = bb_to_IR ( vta->guest_extents,
vta->callback_opaque,
disInstrFn,
vta->guest_bytes,
host_is_bigendian,
vta->arch_guest,
&vta->archinfo_guest,
- &vta->miscinfo_both,
+ &vta->abiinfo_both,
guest_word_type,
vta->do_self_check,
vta->preamble_function,
vexAllocSanityCheck();
- if (irbb == NULL) {
+ if (irsb == NULL) {
/* Access failure. */
vexSetAllocModeTEMP_and_clear();
vex_traceflags = 0;
}
/* Sanity check the initial IR. */
- sanityCheckIRBB( irbb, "initial IR",
+ sanityCheckIRSB( irsb, "initial IR",
False/*can be non-flat*/, guest_word_type );
vexAllocSanityCheck();
/* Clean it up, hopefully a lot. */
- irbb = do_iropt_BB ( irbb, specHelper, preciseMemExnsFn,
+ irsb = do_iropt_BB ( irsb, specHelper, preciseMemExnsFn,
vta->guest_bytes_addr );
- sanityCheckIRBB( irbb, "after initial iropt",
+ sanityCheckIRSB( irsb, "after initial iropt",
True/*must be flat*/, guest_word_type );
if (vex_traceflags & VEX_TRACE_OPT1) {
vex_printf("\n------------------------"
" After pre-instr IR optimisation "
"------------------------\n\n");
- ppIRBB ( irbb );
+ ppIRSB ( irsb );
vex_printf("\n");
}
/* Get the thing instrumented. */
if (vta->instrument1)
- irbb = vta->instrument1(vta->callback_opaque,
- irbb, guest_layout,
+ irsb = vta->instrument1(vta->callback_opaque,
+ irsb, guest_layout,
vta->guest_extents,
guest_word_type, host_word_type);
vexAllocSanityCheck();
if (vta->instrument2)
- irbb = vta->instrument2(vta->callback_opaque,
- irbb, guest_layout,
+ irsb = vta->instrument2(vta->callback_opaque,
+ irsb, guest_layout,
vta->guest_extents,
guest_word_type, host_word_type);
vex_printf("\n------------------------"
" After instrumentation "
"------------------------\n\n");
- ppIRBB ( irbb );
+ ppIRSB ( irsb );
vex_printf("\n");
}
if (vta->instrument1 || vta->instrument2)
- sanityCheckIRBB( irbb, "after instrumentation",
+ sanityCheckIRSB( irsb, "after instrumentation",
True/*must be flat*/, guest_word_type );
/* Do a post-instrumentation cleanup pass. */
if (vta->instrument1 || vta->instrument2) {
- do_deadcode_BB( irbb );
- irbb = cprop_BB( irbb );
- do_deadcode_BB( irbb );
- sanityCheckIRBB( irbb, "after post-instrumentation cleanup",
+ do_deadcode_BB( irsb );
+ irsb = cprop_BB( irsb );
+ do_deadcode_BB( irsb );
+ sanityCheckIRSB( irsb, "after post-instrumentation cleanup",
True/*must be flat*/, guest_word_type );
}
vex_printf("\n------------------------"
" After post-instr IR optimisation "
"------------------------\n\n");
- ppIRBB ( irbb );
+ ppIRSB ( irsb );
vex_printf("\n");
}
/* Turn it into virtual-registerised code. Build trees -- this
also throws away any dead bindings. */
- ado_treebuild_BB( irbb );
+ ado_treebuild_BB( irsb );
vexAllocSanityCheck();
vex_printf("\n------------------------"
" After tree-building "
"------------------------\n\n");
- ppIRBB ( irbb );
+ ppIRSB ( irsb );
vex_printf("\n");
}
" Instruction selection "
"------------------------\n");
- vcode = iselBB ( irbb, vta->arch_host, &vta->archinfo_host,
- &vta->miscinfo_both );
+ vcode = iselSB ( irsb, vta->arch_host, &vta->archinfo_host,
+ &vta->abiinfo_both );
vexAllocSanityCheck();
vai->ppc_cache_line_szB = 0;
}
-/* Write default settings info *vmi. */
-void LibVEX_default_VexMiscInfo ( /*OUT*/VexMiscInfo* vmi )
+/* Write default settings info *vbi. */
+void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi )
{
- vmi->guest_stack_redzone_size = 0;
- vmi->guest_ppc_zap_RZ_at_blr = False;
- vmi->guest_ppc_zap_RZ_at_bl = NULL;
- vmi->guest_ppc_sc_continues_at_LR = False;
- vmi->host_ppc_calls_use_fndescrs = False;
- vmi->host_ppc32_regalign_int64_args = False;
+ vbi->guest_stack_redzone_size = 0;
+ vbi->guest_ppc_zap_RZ_at_blr = False;
+ vbi->guest_ppc_zap_RZ_at_bl = NULL;
+ vbi->guest_ppc_sc_continues_at_LR = False;
+ vbi->host_ppc_calls_use_fndescrs = False;
+ vbi->host_ppc32_regalign_int64_args = False;
}
reg if it is even-numbered? True => yes, False => no. */
Bool host_ppc32_regalign_int64_args;
}
- VexMiscInfo;
+ VexAbiInfo;
-/* Write default settings info *vmi. */
+/* Write default settings info *vbi. */
extern
-void LibVEX_default_VexMiscInfo ( /*OUT*/VexMiscInfo* vmi );
+void LibVEX_default_VexAbiInfo ( /*OUT*/VexAbiInfo* vbi );
/*-------------------------------------------------------*/
VexArchInfo archinfo_guest;
VexArch arch_host;
VexArchInfo archinfo_host;
- VexMiscInfo miscinfo_both;
+ VexAbiInfo abiinfo_both;
/* IN: an opaque value which is passed as the first arg to all
callback functions supplied in this struct. Vex has no idea
/* IN: optionally, two instrumentation functions. May be
NULL. */
- IRBB* (*instrument1) ( /*callback_opaque*/void*,
- IRBB*,
+ IRSB* (*instrument1) ( /*callback_opaque*/void*,
+ IRSB*,
VexGuestLayout*,
VexGuestExtents*,
IRType gWordTy, IRType hWordTy );
- IRBB* (*instrument2) ( /*callback_opaque*/void*,
- IRBB*,
+ IRSB* (*instrument2) ( /*callback_opaque*/void*,
+ IRSB*,
VexGuestLayout*,
VexGuestExtents*,
IRType gWordTy, IRType hWordTy );
disassemble any instructions into it; this is indicated by
the callback returning True.
*/
- Bool (*preamble_function)(/*callback_opaque*/void*, IRBB*);
+ Bool (*preamble_function)(/*callback_opaque*/void*, IRSB*);
/* IN: debug: trace vex activity at various points */
Int traceflags;
Code blocks
~~~~~~~~~~~
- The code is broken into small code blocks (type: 'IRBB'). Each
- code block typically represents from 1 to perhaps 50 instructions.
- IRBBs are single-entry, multiple-exit code blocks. Each IRBB
- contains three things:
+ The code is broken into small code blocks ("superblocks", type:
+ 'IRSB'). Each code block typically represents from 1 to perhaps 50
+ instructions. IRSBs are single-entry, multiple-exit code blocks.
+ Each IRSB contains three things:
- a type environment, which indicates the type of each temporary
- value present in the IRBB
+ value present in the IRSB
- a list of statements, which represent code
- - a jump that exits from the end the IRBB
+ - a jump that exits from the end the IRSB
Because the blocks are multiple-exit, there can be additional
- conditional exit statements that cause control to leave the IRBB
- before the final exit.
+ conditional exit statements that cause control to leave the IRSB
+ before the final exit. Also because of this, IRSBs can cover
+ multiple non-consecutive sequences of code (up to 3). These are
+ recorded in the type VexGuestExtents (see libvex.h).
Statements and expressions
~~~~~~~~~~~~~~~~~~~~~~~~~~
The basic "Get" and "Put" operations are sufficient to model normal
fixed registers on the guest. Selected areas of the guest state
- can be treated as a circular array of registers (type: 'IRArray'),
- which can be indexed at run-time. This is done with the "GetI" and
- "PutI" primitives. This is necessary to describe rotating register
- files, for example the x87 FPU stack, SPARC register windows, and
- the Itanium register files.
+ can be treated as a circular array of registers (type:
+ 'IRRegArray'), which can be indexed at run-time. This is done with
+ the "GetI" and "PutI" primitives. This is necessary to describe
+ rotating register files, for example the x87 FPU stack, SPARC
+ register windows, and the Itanium register files.
Examples, and flattened vs. unflattened code
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
SSAness and typing
~~~~~~~~~~~~~~~~~~
- The IR is fully typed. For every IRBB (IR block) it is possible to
+ The IR is fully typed. For every IRSB (IR block) it is possible to
say unambiguously whether or not it is correctly typed.
Incorrectly typed IR has no meaning and the VEX will refuse to
process it. At various points during processing VEX typechecks the
- eqIRFoo is a structural equality predicate for IRFoos.
- - dopyIRFoo is a deep copy constructor for IRFoos.
+ - deepCopyIRFoo is a deep copy constructor for IRFoos.
It recursively traverses the entire argument tree and
produces a complete new tree.
- - sopyIRFoo is the shallow copy constructor for IRFoos.
+ - shallowCopyIRFoo is the shallow copy constructor for IRFoos.
It creates a new top-level copy of the supplied object,
but does not copy any sub-objects.
*/
extern IRConst* IRConst_V128 ( UShort );
/* Deep-copy an IRConst */
-extern IRConst* dopyIRConst ( IRConst* );
+extern IRConst* deepCopyIRConst ( IRConst* );
/* Pretty-print an IRConst */
extern void ppIRConst ( IRConst* );
extern IRCallee* mkIRCallee ( Int regparms, HChar* name, void* addr );
/* Deep-copy an IRCallee. */
-extern IRCallee* dopyIRCallee ( IRCallee* );
+extern IRCallee* deepCopyIRCallee ( IRCallee* );
/* Pretty-print an IRCallee. */
extern void ppIRCallee ( IRCallee* );
IRType elemTy; /* type of each element in the indexed area */
Int nElems; /* number of elements in the indexed area */
}
- IRArray;
+ IRRegArray;
-extern IRArray* mkIRArray ( Int, IRType, Int );
+extern IRRegArray* mkIRRegArray ( Int, IRType, Int );
-extern IRArray* dopyIRArray ( IRArray* );
+extern IRRegArray* deepCopyIRRegArray ( IRRegArray* );
-extern void ppIRArray ( IRArray* );
-extern Bool eqIRArray ( IRArray*, IRArray* );
+extern void ppIRRegArray ( IRRegArray* );
+extern Bool eqIRRegArray ( IRRegArray*, IRRegArray* );
/* ------------------ Temporaries ------------------ */
Iex_Binder,
Iex_Get,
Iex_GetI,
- Iex_Tmp,
+ Iex_RdTmp,
Iex_Qop,
Iex_Triop,
Iex_Binop,
example is the x87 FP register stack.
The part of the guest state to be treated as a circular array
- is described in the IRArray 'descr' field. It holds the
+ is described in the IRRegArray 'descr' field. It holds the
offset of the first element in the array, the type of each
element, and the number of elements.
eg. GETI(128:8xI8)[t1,0]
*/
struct {
- IRArray* descr; /* Part of guest state treated as circular */
- IRExpr* ix; /* Variable part of index into array */
- Int bias; /* Constant offset part of index into array */
+ IRRegArray* descr; /* Part of guest state treated as circular */
+ IRExpr* ix; /* Variable part of index into array */
+ Int bias; /* Constant offset part of index into array */
} GetI;
/* The value held by a temporary.
*/
struct {
IRTemp tmp; /* The temporary number */
- } Tmp;
+ } RdTmp;
/* A quaternary operation.
ppIRExpr output: <op>(<arg1>, <arg2>, <arg3>, <arg4>),
/* Expression constructors. */
extern IRExpr* IRExpr_Binder ( Int binder );
extern IRExpr* IRExpr_Get ( Int off, IRType ty );
-extern IRExpr* IRExpr_GetI ( IRArray* descr, IRExpr* ix, Int bias );
-extern IRExpr* IRExpr_Tmp ( IRTemp tmp );
+extern IRExpr* IRExpr_GetI ( IRRegArray* descr, IRExpr* ix, Int bias );
+extern IRExpr* IRExpr_RdTmp ( IRTemp tmp );
extern IRExpr* IRExpr_Qop ( IROp op, IRExpr* arg1, IRExpr* arg2,
IRExpr* arg3, IRExpr* arg4 );
extern IRExpr* IRExpr_Triop ( IROp op, IRExpr* arg1,
extern IRExpr* IRExpr_Mux0X ( IRExpr* cond, IRExpr* expr0, IRExpr* exprX );
/* Deep-copy an IRExpr. */
-extern IRExpr* dopyIRExpr ( IRExpr* );
+extern IRExpr* deepCopyIRExpr ( IRExpr* );
/* Pretty-print an IRExpr. */
extern void ppIRExpr ( IRExpr* );
IRExpr*, IRExpr*, IRExpr* );
/* IRExpr copiers:
- - sopy: shallow-copy (ie. create a new vector that shares the
+ - shallowCopy: shallow-copy (ie. create a new vector that shares the
elements with the original).
- - dopy: deep-copy (ie. create a completely new vector). */
-extern IRExpr** sopyIRExprVec ( IRExpr** );
-extern IRExpr** dopyIRExprVec ( IRExpr** );
+ - deepCopy: deep-copy (ie. create a completely new vector). */
+extern IRExpr** shallowCopyIRExprVec ( IRExpr** );
+extern IRExpr** deepCopyIRExprVec ( IRExpr** );
/* Make a constant expression from the given host word taking into
account (of course) the host word size. */
/* Convenience functions for atoms (IRExprs which are either Iex_Tmp or
* Iex_Const). */
static inline Bool isIRAtom ( IRExpr* e ) {
- return toBool(e->tag == Iex_Tmp || e->tag == Iex_Const);
+ return toBool(e->tag == Iex_RdTmp || e->tag == Iex_Const);
}
/* Are these two IR atoms identical? Causes an assertion
extern IRDirty* emptyIRDirty ( void );
/* Deep-copy a dirty call */
-extern IRDirty* dopyIRDirty ( IRDirty* );
+extern IRDirty* deepCopyIRDirty ( IRDirty* );
/* A handy function which takes some of the tedium out of constructing
dirty helper calls. The called function impliedly does not return
Ist_AbiHint, /* META */
Ist_Put,
Ist_PutI,
- Ist_Tmp,
+ Ist_WrTmp,
Ist_Store,
Ist_Dirty,
Ist_MFence,
/* META: instruction mark. Marks the start of the statements
that represent a single machine instruction (the end of
those statements is marked by the next IMark or the end of
- the IRBB). Contains the address and length of the
+ the IRSB). Contains the address and length of the
instruction.
ppIRExpr output: ------ IMark(<addr>, <len>) ------,
eg. PUTI(64:8xF64)[t5,0] = t1
*/
struct {
- IRArray* descr; /* Part of guest state treated as circular */
- IRExpr* ix; /* Variable part of index into array */
- Int bias; /* Constant offset part of index into array */
- IRExpr* data; /* The value to write */
+ IRRegArray* descr; /* Part of guest state treated as circular */
+ IRExpr* ix; /* Variable part of index into array */
+ Int bias; /* Constant offset part of index into array */
+ IRExpr* data; /* The value to write */
} PutI;
- /* Assign a value to a temporary. ("Tmp" is not a very good
- name for this, particularly because there is also a Tmp
- expression kind.)
+ /* Assign a value to a temporary. Note that SSA rules require
+ each tmp is only assigned to once. IR sanity checking will
+ reject any block containing a temporary which is not assigned
+ to exactly once.
ppIRExpr output: t<tmp> = <data>, eg. t1 = 3
*/
struct {
IRTemp tmp; /* Temporary (LHS of assignment) */
IRExpr* data; /* Expression (RHS of assignment) */
- } Tmp;
+ } WrTmp;
/* Write a value to memory.
ppIRExpr output: ST<end>(<addr>) = <data>, eg. STle(t1) = t2
struct {
} MFence;
- /* Conditional exit from the middle of an IRBB.
+ /* Conditional exit from the middle of an IRSB.
ppIRExpr output: if (<guard>) goto {<jk>} <dst>
eg. if (t69) goto {Boring} 0x4000AAA:I32
*/
extern IRStmt* IRStmt_IMark ( Addr64 addr, Int len );
extern IRStmt* IRStmt_AbiHint ( IRExpr* base, Int len );
extern IRStmt* IRStmt_Put ( Int off, IRExpr* data );
-extern IRStmt* IRStmt_PutI ( IRArray* descr, IRExpr* ix, Int bias,
+extern IRStmt* IRStmt_PutI ( IRRegArray* descr, IRExpr* ix, Int bias,
IRExpr* data );
-extern IRStmt* IRStmt_Tmp ( IRTemp tmp, IRExpr* data );
+extern IRStmt* IRStmt_WrTmp ( IRTemp tmp, IRExpr* data );
extern IRStmt* IRStmt_Store ( IREndness end, IRExpr* addr, IRExpr* data );
extern IRStmt* IRStmt_Dirty ( IRDirty* details );
extern IRStmt* IRStmt_MFence ( void );
extern IRStmt* IRStmt_Exit ( IRExpr* guard, IRJumpKind jk, IRConst* dst );
/* Deep-copy an IRStmt. */
-extern IRStmt* dopyIRStmt ( IRStmt* );
+extern IRStmt* deepCopyIRStmt ( IRStmt* );
/* Pretty-print an IRStmt. */
extern void ppIRStmt ( IRStmt* );
extern IRTemp newIRTemp ( IRTypeEnv*, IRType );
/* Deep-copy a type environment */
-extern IRTypeEnv* dopyIRTypeEnv ( IRTypeEnv* );
+extern IRTypeEnv* deepCopyIRTypeEnv ( IRTypeEnv* );
/* Pretty-print a type environment */
extern void ppIRTypeEnv ( IRTypeEnv* );
-/* Code blocks contain:
+/* Code blocks, which in proper compiler terminology are superblocks
+ (single entry, multiple exit code sequences) contain:
+
- A table giving a type for each temp (the "type environment")
- An expandable array of statements
- An expression of type 32 or 64 bits, depending on the
- guest's word size, indicating the next destination.
+ guest's word size, indicating the next destination if the block
+ executes all the way to the end, without a side exit
- An indication of any special actions (JumpKind) needed
for this final jump.
- The "BB" is short for "basic block", but this is a misnomer, as an
- IRBB can contain multiple exits.
+ "IRSB" stands for "IR Super Block".
*/
typedef
struct {
IRExpr* next;
IRJumpKind jumpkind;
}
- IRBB;
+ IRSB;
-/* Allocate a new, uninitialised IRBB */
-extern IRBB* emptyIRBB ( void );
+/* Allocate a new, uninitialised IRSB */
+extern IRSB* emptyIRSB ( void );
-/* Deep-copy an IRBB */
-extern IRBB* dopyIRBB ( IRBB* );
+/* Deep-copy an IRSB */
+extern IRSB* deepCopyIRSB ( IRSB* );
-/* Deep-copy an IRBB, except for the statements list, which set to be
+/* Deep-copy an IRSB, except for the statements list, which set to be
a new, empty, list of statements. */
-extern IRBB* dopyIRBBExceptStmts ( IRBB* );
+extern IRSB* deepCopyIRSBExceptStmts ( IRSB* );
-/* Pretty-print an IRBB */
-extern void ppIRBB ( IRBB* );
+/* Pretty-print an IRSB */
+extern void ppIRSB ( IRSB* );
-/* Append an IRStmt to an IRBB */
-extern void addStmtToIRBB ( IRBB*, IRStmt* );
+/* Append an IRStmt to an IRSB */
+extern void addStmtToIRSB ( IRSB*, IRStmt* );
/*---------------------------------------------------------------*/
extern IRType typeOfIRExpr ( IRTypeEnv*, IRExpr* );
/* Sanity check a BB of IR */
-extern void sanityCheckIRBB ( IRBB* bb,
+extern void sanityCheckIRSB ( IRSB* bb,
HChar* caller,
Bool require_flatness,
IRType guest_word_size );
VexControl vcon;
VexGuestExtents vge;
VexArchInfo vai_x86, vai_amd64, vai_ppc32;
- VexMiscInfo vmi;
+ VexAbiInfo vbi;
VexTranslateArgs vta;
if (argc != 2) {
vai_ppc32.hwcaps = 0;
vai_ppc32.ppc_cache_line_szB = 128;
- LibVEX_default_VexMiscInfo(&vmi);
+ LibVEX_default_VexAbiInfo(&vbi);
/* ----- Set up args for LibVEX_Translate ----- */
#if 1 /* ppc32 -> ppc32 */
vta.arch_host = VexArchX86;
vta.archinfo_host = vai_x86;
#endif
- vta.miscinfo_both = vmi;
+ vta.abiinfo_both = vbi;
vta.guest_bytes = origbuf;
vta.guest_bytes_addr = (Addr64)orig_addr;
vta.callback_opaque = NULL;
projects / thirdparty / valgrind.git / commitdiff
