compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x10000>,
<0 0x11f50000 0 0x1000>;
- interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC50_0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0>,
<&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>,
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11eb0000 0 0x1000>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1>,
<&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
compatible = "mediatek,mt8188-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11e60000 0 0x1000>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupts-extended = <&gic GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
clocks = <&topckgen CLK_TOP_MSDC30_2>,
<&infracfg_ao CLK_INFRA_AO_MSDC2>,
<&infracfg_ao CLK_INFRA_AO_MSDC30_2>;