RISC-V: fix const interleaved stepped vector with a scalar pattern

When bisecting for ICE in PR/117353, commit 771256bcb9dd ("RISC-V: Emit costs for
bool and stepped const vectors") uncovered yet another latent issue (first noted [1])

  [1] https://github.com/patrick-rivos/gcc-postcommit-ci/issues/1625

This patch fixes some of the fortran regressions from that report.

Fixes 71a5ac6703d1 ("RISC-V: Support interleave vector with different step sequence")

rv64imafdcv_zvl256b_zba_zbb_zbs_zicond/lp64d/medlow
                            | # of unexpected case / # of unique unexpected case
                            |          gcc |          g++ |     gfortran |
                            |  392 /   108 |    7 /     3 |   91 /    24 |
                            |  392 /   108 |    7 /     3 |   67 /    12 |

gcc/ChangeLog:

	* config/riscv/riscv-v.cc (expand_const_vector): Use IOR op.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/slp-interleave-5.c: New test.

Tested-by: Edwin Lu <ewlu@rivosinc.com> # Pre-commit CU #2503
Signed-off-by: Vineet Gupta <vineetg@rivosinc.com>

diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 209b7ee88f18b0e42661f1b44c662d7deea88af9..5e728f04cf51a013b4d4ad24d8ec6a0f7da579df 100644 (file)
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -1501,9 +1501,9 @@ expand_const_vector (rtx target, rtx src)
                    gen_int_mode (builder.inner_bits_size (), new_smode),
                    NULL_RTX, false, OPTAB_DIRECT);
                  rtx tmp2 = gen_reg_rtx (new_mode);
-                 rtx and_ops[] = {tmp2, tmp1, scalar};
-                 emit_vlmax_insn (code_for_pred_scalar (AND, new_mode),
-                                  BINARY_OP, and_ops);
+                 rtx ior_ops[] = {tmp2, tmp1, scalar};
+                 emit_vlmax_insn (code_for_pred_scalar (IOR, new_mode),
+                                  BINARY_OP, ior_ops);
                  emit_move_insn (result, gen_lowpart (mode, tmp2));
                }
              else

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c
new file mode 100644 (file)
index 0000000..32cfe8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/slp-interleave-5.c
@@ -0,0 +1,35 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv_zvl1024b -mabi=lp64d -O3 -fdump-tree-optimized-details" } */
+
+struct S { int a, b; } s[8];
+
+void
+foo ()
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      s[i].b = 1;
+      s[i].a = i+1;
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "\{ 1, 1, 2, 1, 3, 1, 4, 1 \}" 1 "optimized" } } */
+/* { dg-final { scan-assembler {vid\.v} } } */
+/* { dg-final { scan-assembler {vadd\.v} } } */
+/* { dg-final { scan-assembler {vor\.v} } } */
+
+void
+foo2 ()
+{
+  int i;
+  for (i = 0; i < 8; i++)
+    {
+      s[i].b = 0;
+      s[i].a = i+1;
+    }
+}
+
+/* { dg-final { scan-tree-dump-times "\{ 1, 0, 2, 0, 3, 0, 4, 0 \}" 1 "optimized" } } */
+/* { dg-final { scan-assembler {vid\.v} } } */
+/* { dg-final { scan-assembler {vadd\.v} } } */