riscv: dts: sophgo: sg2044: Add clock controller device

Add clock controller and pll clock node for sg2044.

Link: https://lore.kernel.org/r/20250608232836.784737-3-inochiama@gmail.com
Signed-off-by: Inochi Amaoto <inochiama@gmail.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Chen Wang <wangchen20@iscas.ac.cn>

diff --git a/arch/riscv/boot/dts/sophgo/sg2044.dtsi b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
index a0c13d8d26af2fd266f551658f39e65fa46cfadd..d21a59948186f8d2f114b9b0cf600fb37f3ab7db 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2044.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2044.dtsi
@@ -3,6 +3,8 @@
  * Copyright (C) 2025 Inochi Amaoto <inochiama@gmail.com>
  */
 
+#include <dt-bindings/clock/sophgo,sg2044-pll.h>
+#include <dt-bindings/clock/sophgo,sg2044-clk.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 
 #include "sg2044-cpus.dtsi"
@@ -32,6 +34,9 @@
                        compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
                        reg = <0x70 0x30000000 0x0 0x1000>;
                        clock-frequency = <500000000>;
+                       clocks = <&clk CLK_GATE_UART_500M>,
+                                <&clk CLK_GATE_APB_UART>;
+                       clock-names = "baudclk", "apb_pclk";
                        interrupt-parent = <&intc>;
                        interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
@@ -44,6 +49,9 @@
                        compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
                        reg = <0x70 0x30001000 0x0 0x1000>;
                        clock-frequency = <500000000>;
+                       clocks = <&clk CLK_GATE_UART_500M>,
+                                <&clk CLK_GATE_APB_UART>;
+                       clock-names = "baudclk", "apb_pclk";
                        interrupt-parent = <&intc>;
                        interrupts = <42 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
@@ -56,6 +64,9 @@
                        compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
                        reg = <0x70 0x30002000 0x0 0x1000>;
                        clock-frequency = <500000000>;
+                       clocks = <&clk CLK_GATE_UART_500M>,
+                                <&clk CLK_GATE_APB_UART>;
+                       clock-names = "baudclk", "apb_pclk";
                        interrupt-parent = <&intc>;
                        interrupts = <43 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
@@ -68,6 +79,9 @@
                        compatible = "sophgo,sg2044-uart", "snps,dw-apb-uart";
                        reg = <0x70 0x30003000 0x0 0x1000>;
                        clock-frequency = <500000000>;
+                       clocks = <&clk CLK_GATE_UART_500M>,
+                                <&clk CLK_GATE_APB_UART>;
+                       clock-names = "baudclk", "apb_pclk";
                        interrupt-parent = <&intc>;
                        interrupts = <44 IRQ_TYPE_LEVEL_HIGH>;
                        reg-shift = <2>;
@@ -83,6 +97,26 @@
                        clocks = <&osc>;
                };
 
+               clk: clock-controller@7050002000 {
+                       compatible = "sophgo,sg2044-clk";
+                       reg = <0x70 0x50002000 0x0 0x1000>;
+                       #clock-cells = <1>;
+                       clocks = <&syscon CLK_FPLL0>, <&syscon CLK_FPLL1>,
+                                <&syscon CLK_FPLL2>, <&syscon CLK_DPLL0>,
+                                <&syscon CLK_DPLL1>, <&syscon CLK_DPLL2>,
+                                <&syscon CLK_DPLL3>, <&syscon CLK_DPLL4>,
+                                <&syscon CLK_DPLL5>, <&syscon CLK_DPLL6>,
+                                <&syscon CLK_DPLL7>, <&syscon CLK_MPLL0>,
+                                <&syscon CLK_MPLL1>, <&syscon CLK_MPLL2>,
+                                <&syscon CLK_MPLL3>, <&syscon CLK_MPLL4>,
+                                <&syscon CLK_MPLL5>;
+                       clock-names = "fpll0", "fpll1", "fpll2", "dpll0",
+                                     "dpll1", "dpll2", "dpll3", "dpll4",
+                                     "dpll5", "dpll6", "dpll7", "mpll0",
+                                     "mpll1", "mpll2", "mpll3", "mpll4",
+                                     "mpll5";
+               };
+
                rst: reset-controller@7050003000 {
                        compatible = "sophgo,sg2044-reset",
                                     "sophgo,sg2042-reset";