drm/amd/display: Rework YCbCr422 DSC policy

- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSC
enabled based on DSC caps and stream signal type

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 1dd0a2cf786cb7a494284f5f4352724173210eec..2bb4c7751c0176d502b25da16ed954bcf605aea1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -563,6 +563,7 @@ struct dc_config {
        bool frame_update_cmd_version2;
        struct spl_sharpness_range dcn_sharpness_range;
        struct spl_sharpness_range dcn_override_sharpness_range;
+       bool no_native422_support;
 };
 
 enum visual_confirm {
@@ -987,7 +988,6 @@ struct link_service;
  * causing an issue or not.
  */
 struct dc_debug_options {
-       bool native422_support;
        bool disable_dsc;
        enum visual_confirm visual_confirm;
        int visual_confirm_rect_height;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
index 9d18f1c080791a97145032886903601a6d1a6eba..101bce6b8de64f703e220a1c0c5ce1a25300e9fe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h
@@ -52,6 +52,7 @@ struct dc_dsc_policy {
        uint32_t max_target_bpp;
        uint32_t min_target_bpp;
        bool enable_dsc_when_not_needed;
+       bool ycbcr422_simple;
 };
 
 struct dc_dsc_config_options {

diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
index d834cb595afab78b2f29f7fca3c30ce23d583ec2..e25b88f2d6b9dbf3000c94b58de31e9e3b3c765c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
@@ -1174,12 +1174,12 @@ static unsigned int map_plane_to_dml_display_cfg(const struct dml2_context *dml2
                const struct dc_state *context, const struct dml_display_cfg_st *dml_dispcfg, unsigned int stream_id, int plane_index)
 {
        unsigned int plane_id;
-       int i = 0;
-       int location = -1;
+       unsigned int i = 0;
+       unsigned int location = UINT_MAX;
 
        if (!get_plane_id(context->bw_ctx.dml2, context, plane, stream_id, plane_index, &plane_id)) {
                ASSERT(false);
-               return -1;
+               return UINT_MAX;
        }
 
        for (i = 0; i < __DML2_WRAPPER_MAX_STREAMS_PLANES__; i++) {

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
index 5b3584ad5b6b3d14f146dcae6ff483b3d4be3f48..8dfb6dd14eb297923e0b239ad5651cbad8616c81 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c
@@ -680,9 +680,6 @@ static void get_dsc_enc_caps(
        } else {
                build_dsc_enc_caps(dsc, dsc_enc_caps);
        }
-
-       if (dsc->ctx->dc->debug.native422_support)
-               dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
 }
 
 /* Returns 'false' if no intersection was found for at least one capability.
@@ -1100,13 +1097,14 @@ static bool setup_dsc_config(
                branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_0_mps;
                break;
        case PIXEL_ENCODING_YCBCR422:
-               is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;
-               sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;
-               branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;
-               if (!is_dsc_possible) {
+               if (policy.ycbcr422_simple) {
                        is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_SIMPLE_422;
                        dsc_cfg->ycbcr422_simple = is_dsc_possible;
                        sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_0_mps;
+               } else {
+                       is_dsc_possible = (bool)dsc_common_caps.color_formats.bits.YCBCR_NATIVE_422;
+                       sink_per_slice_throughput_mps = dsc_sink_caps->throughput_mode_1_mps;
+                       branch_max_throughput_mps = dsc_sink_caps->branch_overall_throughput_1_mps;
                }
                break;
        case PIXEL_ENCODING_YCBCR420:
@@ -1406,6 +1404,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
                policy->min_target_bpp = 8;
                /* DP specs limits to 3 x bpc */
                policy->max_target_bpp = 3 * bpc;
+               policy->ycbcr422_simple = true;
                break;
        case PIXEL_ENCODING_YCBCR420:
                /* DP specs limits to 6 */

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
index 242f1e6f0d8f723778643aa6e9017e3705c8547f..6e1e759462bf9569c093c931496a0e60ff0d0631 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
@@ -100,7 +100,7 @@ void dsc2_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz)
        dsc_enc_caps->color_formats.bits.RGB = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
-       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
+       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
 
        dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
index e712985f7abdbcc16f71f4796f814f0296b19fb3..17acb64a9d8041367b37b31f9b09325a207ce965 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
@@ -128,7 +128,7 @@ void dsc35_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsigned int m
        dsc_enc_caps->color_formats.bits.RGB = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
-       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
+       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
 
        dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
index c1bdbb38c690b803b4a99dc461e10cae22ef6369..bbb8b5b18a4e6b087958cf861756cff5758c706b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
@@ -78,7 +78,7 @@ static void dsc401_get_single_enc_caps(struct dsc_enc_caps *dsc_enc_caps, unsign
        dsc_enc_caps->color_formats.bits.RGB = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_444 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_SIMPLE_422 = 1;
-       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 0;
+       dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_422 = 1;
        dsc_enc_caps->color_formats.bits.YCBCR_NATIVE_420 = 1;
 
        dsc_enc_caps->color_depth.bits.COLOR_DEPTH_8_BPC = 1;

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index f992c2d167487c0c2eda2c7c19777124e9d27c7d..7f1761080aba0ec46aca6aeb2d2168e079de242a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -781,7 +781,6 @@ static void restore_phy_clocks_for_destructive_link_verification(const struct dc
 }
 
 static void verify_link_capability_destructive(struct dc_link *link,
-               struct dc_sink *sink,
                enum dc_detect_reason reason)
 {
        bool should_prepare_phy_clocks =
@@ -855,11 +854,11 @@ static bool should_verify_link_capability_destructively(struct dc_link *link,
        return destrictive;
 }
 
-static void verify_link_capability(struct dc_link *link, struct dc_sink *sink,
+static void verify_link_capability(struct dc_link *link,
                enum dc_detect_reason reason)
 {
        if (should_verify_link_capability_destructively(link, reason))
-               verify_link_capability_destructive(link, sink, reason);
+               verify_link_capability_destructive(link, reason);
        else
                verify_link_capability_non_destructive(link);
 }
@@ -1453,8 +1452,9 @@ bool link_detect(struct dc_link *link, enum dc_detect_reason reason)
 
        is_local_sink_detect_success = detect_link_and_local_sink(link, reason);
 
-       if (is_local_sink_detect_success && link->local_sink)
-               verify_link_capability(link, link->local_sink, reason);
+       if (is_local_sink_detect_success && link->local_sink) {
+               verify_link_capability(link, reason);
+       }
 
        DC_LOG_DC("%s: link_index=%d is_local_sink_detect_success=%d pre_link_type=%d link_type=%d\n", __func__,
                                link->link_index, is_local_sink_detect_success, pre_link_type, link->type);

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index b4f46408a0005fd5488703fe09e1a0f818b61b44..e12c25896364a606ff96f5273b63ccf92ad9cbbb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -181,7 +181,8 @@ void link_set_all_streams_dpms_off_for_link(struct dc_link *link)
        /* link can be also enabled by vbios. In this case it is not recorded
         * in pipe_ctx. Disable link phy here to make sure it is completely off
         */
-       dp_disable_link_phy(link, &link_res, link->connector_signal);
+       if (dc_is_dp_signal(link->connector_signal))
+               dp_disable_link_phy(link, &link_res, link->connector_signal);
 }
 
 void link_resume(struct dc_link *link)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 046724c86c7ae794bca47032ee6ac0e30e91c1c6..6ce6b2b1f288a1b0b696d27898cde83869077aca 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -1963,6 +1963,8 @@ static bool dcn31_resource_construct(
        dc->config.use_pipe_ctx_sync_logic = true;
        dc->config.disable_hbr_audio_dp2 = true;
 
+       dc->config.no_native422_support = true;
+
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index 4d5fcd7a0b00678468825352705be3f57070ccd3..0e0c52128c55d699daf466188eac82de0f3d36fe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -1925,6 +1925,8 @@ static bool dcn315_resource_construct(
        dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
        dc->caps.color.mpc.ocsc = 1;
 
+       dc->config.no_native422_support = true;
+
        /* read VBIOS LTTPR caps */
        {
                if (ctx->dc_bios->funcs->get_lttpr_caps) {