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arm: merge MVE_5 and MVE_6 iterators
authorChristophe Lyon <christophe.lyon@linaro.org>
Thu, 25 May 2023 12:19:52 +0000 (12:19 +0000)
committerChristophe Lyon <christophe.lyon@linaro.org>
Thu, 25 May 2023 14:51:28 +0000 (14:51 +0000)
MVE_5 and MVE_6 iterators are the same: this patch replaces MVE_6 with
MVE_5 everywhere in mve.md and removes MVE_6 from iterators.md.

2023-05-25  Christophe Lyon <christophe.lyon@linaro.org>

gcc/
* config/arm/iterators.md (MVE_6): Remove.
* config/arm/mve.md: Replace MVE_6 with MVE_5.

gcc/config/arm/iterators.md patch | blob | blame | history
gcc/config/arm/mve.md patch | blob | blame | history

diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index 597c1dae640c93bf80e3882db56832f12b9e85e8..9e77af55d60ad5516bd340d7c739b006177be4da 100644 (file)
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -272,7 +272,6 @@
 (define_mode_iterator MVE_3 [V16QI V8HI])
 (define_mode_iterator MVE_2 [V16QI V8HI V4SI])
 (define_mode_iterator MVE_5 [V8HI V4SI])
-(define_mode_iterator MVE_6 [V8HI V4SI])
 (define_mode_iterator MVE_7 [V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI V2QI])
 (define_mode_iterator MVE_V8HF [V8HF])
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index 9e3570c526438aecba8d9dffbb18879d67cc3d94..74909ce47e132c22a94f7d9cd3a0921b38e33051 100644 (file)
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -3732,9 +3732,9 @@
 ;; [vldrhq_gather_offset_s vldrhq_gather_offset_u]
 ;;
 (define_insn "mve_vldrhq_gather_offset_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
-                      (match_operand:MVE_6 2 "s_register_operand" "w")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_5 2 "s_register_operand" "w")]
        VLDRHGOQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3755,9 +3755,9 @@
 ;; [vldrhq_gather_offset_z_s vldrhq_gather_offset_z_u]
 ;;
 (define_insn "mve_vldrhq_gather_offset_z_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
-                      (match_operand:MVE_6 2 "s_register_operand" "w")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")
        ]VLDRHGOQ))
   ]
@@ -3780,9 +3780,9 @@
 ;; [vldrhq_gather_shifted_offset_s vldrhq_gather_shifted_offset_u]
 ;;
 (define_insn "mve_vldrhq_gather_shifted_offset_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
-                      (match_operand:MVE_6 2 "s_register_operand" "w")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_5 2 "s_register_operand" "w")]
        VLDRHGSOQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3803,9 +3803,9 @@
 ;; [vldrhq_gather_shifted_offset_z_s vldrhq_gather_shited_offset_z_u]
 ;;
 (define_insn "mve_vldrhq_gather_shifted_offset_z_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=&w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
-                      (match_operand:MVE_6 2 "s_register_operand" "w")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=&w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "memory_operand" "Us")
+                      (match_operand:MVE_5 2 "s_register_operand" "w")
                       (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")
        ]VLDRHGSOQ))
   ]
@@ -3828,8 +3828,8 @@
 ;; [vldrhq_s, vldrhq_u]
 ;;
 (define_insn "mve_vldrhq_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")]
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")]
         VLDRHQ))
   ]
   "TARGET_HAVE_MVE"
@@ -3870,8 +3870,8 @@
 ;; [vldrhq_z_s vldrhq_z_u]
 ;;
 (define_insn "mve_vldrhq_z_<supf><mode>"
-  [(set (match_operand:MVE_6 0 "s_register_operand" "=w")
-       (unspec:MVE_6 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")
+  [(set (match_operand:MVE_5 0 "s_register_operand" "=w")
+       (unspec:MVE_5 [(match_operand:<MVE_H_ELEM> 1 "mve_memory_operand" "Ux")
        (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")]
         VLDRHQ))
   ]
@@ -4449,7 +4449,7 @@
 (define_insn "mve_vstrhq_p_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
        (unspec:<MVE_H_ELEM>
-        [(match_operand:MVE_6 1 "s_register_operand" "w")
+        [(match_operand:MVE_5 1 "s_register_operand" "w")
          (match_operand:<MVE_VPRED> 2 "vpr_register_operand" "Up")
          (match_dup 0)]
         VSTRHQ))
@@ -4470,8 +4470,8 @@
 ;;
 (define_expand "mve_vstrhq_scatter_offset_p_<supf><mode>"
   [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
-   (match_operand:MVE_6 1 "s_register_operand")
-   (match_operand:MVE_6 2 "s_register_operand")
+   (match_operand:MVE_5 1 "s_register_operand")
+   (match_operand:MVE_5 2 "s_register_operand")
    (match_operand:<MVE_VPRED> 3 "vpr_register_operand")
    (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
   "TARGET_HAVE_MVE"
@@ -4489,8 +4489,8 @@
   [(set (mem:BLK (scratch))
        (unspec:BLK
          [(match_operand:SI 0 "register_operand" "r")
-          (match_operand:MVE_6 1 "s_register_operand" "w")
-          (match_operand:MVE_6 2 "s_register_operand" "w")
+          (match_operand:MVE_5 1 "s_register_operand" "w")
+          (match_operand:MVE_5 2 "s_register_operand" "w")
           (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
          VSTRHSOQ))]
   "TARGET_HAVE_MVE"
@@ -4502,8 +4502,8 @@
 ;;
 (define_expand "mve_vstrhq_scatter_offset_<supf><mode>"
   [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
-   (match_operand:MVE_6 1 "s_register_operand")
-   (match_operand:MVE_6 2 "s_register_operand")
+   (match_operand:MVE_5 1 "s_register_operand")
+   (match_operand:MVE_5 2 "s_register_operand")
    (unspec:V4SI [(const_int 0)] VSTRHSOQ)]
   "TARGET_HAVE_MVE"
 {
@@ -4518,8 +4518,8 @@
   [(set (mem:BLK (scratch))
        (unspec:BLK
          [(match_operand:SI 0 "register_operand" "r")
-          (match_operand:MVE_6 1 "s_register_operand" "w")
-          (match_operand:MVE_6 2 "s_register_operand" "w")]
+          (match_operand:MVE_5 1 "s_register_operand" "w")
+          (match_operand:MVE_5 2 "s_register_operand" "w")]
          VSTRHSOQ))]
   "TARGET_HAVE_MVE"
   "vstrh.<V_sz_elem>\t%q2, [%0, %q1]"
@@ -4530,8 +4530,8 @@
 ;;
 (define_expand "mve_vstrhq_scatter_shifted_offset_p_<supf><mode>"
   [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
-   (match_operand:MVE_6 1 "s_register_operand")
-   (match_operand:MVE_6 2 "s_register_operand")
+   (match_operand:MVE_5 1 "s_register_operand")
+   (match_operand:MVE_5 2 "s_register_operand")
    (match_operand:<MVE_VPRED> 3 "vpr_register_operand")
    (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
   "TARGET_HAVE_MVE"
@@ -4549,8 +4549,8 @@
   [(set (mem:BLK (scratch))
        (unspec:BLK
          [(match_operand:SI 0 "register_operand" "r")
-          (match_operand:MVE_6 1 "s_register_operand" "w")
-          (match_operand:MVE_6 2 "s_register_operand" "w")
+          (match_operand:MVE_5 1 "s_register_operand" "w")
+          (match_operand:MVE_5 2 "s_register_operand" "w")
           (match_operand:<MVE_VPRED> 3 "vpr_register_operand" "Up")]
          VSTRHSSOQ))]
   "TARGET_HAVE_MVE"
@@ -4562,8 +4562,8 @@
 ;;
 (define_expand "mve_vstrhq_scatter_shifted_offset_<supf><mode>"
   [(match_operand:<MVE_H_ELEM> 0 "mve_scatter_memory")
-   (match_operand:MVE_6 1 "s_register_operand")
-   (match_operand:MVE_6 2 "s_register_operand")
+   (match_operand:MVE_5 1 "s_register_operand")
+   (match_operand:MVE_5 2 "s_register_operand")
    (unspec:V4SI [(const_int 0)] VSTRHSSOQ)]
   "TARGET_HAVE_MVE"
 {
@@ -4579,8 +4579,8 @@
   [(set (mem:BLK (scratch))
        (unspec:BLK
          [(match_operand:SI 0 "register_operand" "r")
-          (match_operand:MVE_6 1 "s_register_operand" "w")
-          (match_operand:MVE_6 2 "s_register_operand" "w")]
+          (match_operand:MVE_5 1 "s_register_operand" "w")
+          (match_operand:MVE_5 2 "s_register_operand" "w")]
          VSTRHSSOQ))]
   "TARGET_HAVE_MVE"
   "vstrh.<V_sz_elem>\t%q2, [%0, %q1, uxtw #1]"
@@ -4591,7 +4591,7 @@
 ;;
 (define_insn "mve_vstrhq_<supf><mode>"
   [(set (match_operand:<MVE_H_ELEM> 0 "mve_memory_operand" "=Ux")
-       (unspec:<MVE_H_ELEM> [(match_operand:MVE_6 1 "s_register_operand" "w")]
+       (unspec:<MVE_H_ELEM> [(match_operand:MVE_5 1 "s_register_operand" "w")]
         VSTRHQ))
   ]
   "TARGET_HAVE_MVE"
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