]> git.ipfire.org Git - thirdparty/linux.git/commitdiff
dt-bindings: clock: Convert maxim,max9485 to DT schema
authorRob Herring (Arm) <robh@kernel.org>
Mon, 30 Jun 2025 23:26:57 +0000 (18:26 -0500)
committerStephen Boyd <sboyd@kernel.org>
Thu, 24 Jul 2025 21:11:26 +0000 (14:11 -0700)
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250630232658.3701225-1-robh@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Documentation/devicetree/bindings/clock/maxim,max9485.txt [deleted file]
Documentation/devicetree/bindings/clock/maxim,max9485.yaml [new file with mode: 0644]

diff --git a/Documentation/devicetree/bindings/clock/maxim,max9485.txt b/Documentation/devicetree/bindings/clock/maxim,max9485.txt
deleted file mode 100644 (file)
index b8f5c3b..0000000
+++ /dev/null
@@ -1,59 +0,0 @@
-Devicetree bindings for Maxim MAX9485 Programmable Audio Clock Generator
-
-This device exposes 4 clocks in total:
-
-- MAX9485_MCLKOUT:     A gated, buffered output of the input clock of 27 MHz
-- MAX9485_CLKOUT:      A PLL that can be configured to 16 different discrete
-                       frequencies
-- MAX9485_CLKOUT[1,2]: Two gated outputs for MAX9485_CLKOUT
-
-MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
-requests.
-
-Required properties:
-- compatible:  "maxim,max9485"
-- clocks:      Input clock, must provide 27.000 MHz
-- clock-names: Must be set to "xclk"
-- #clock-cells: From common clock binding; shall be set to 1
-
-Optional properties:
-- reset-gpios:         GPIO descriptor connected to the #RESET input pin
-- vdd-supply:          A regulator node for Vdd
-- clock-output-names:  Name of output clocks, as defined in common clock
-                       bindings
-
-If not explicitly set, the output names are "mclkout", "clkout", "clkout1"
-and "clkout2".
-
-Clocks are defined as preprocessor macros in the dt-binding header.
-
-Example:
-
-       #include <dt-bindings/clock/maxim,max9485.h>
-
-       xo-27mhz: xo-27mhz {
-               compatible = "fixed-clock";
-               #clock-cells = <0>;
-               clock-frequency = <27000000>;
-       };
-
-       &i2c0 {
-               max9485: audio-clock@63 {
-                       reg = <0x63>;
-                       compatible = "maxim,max9485";
-                       clock-names = "xclk";
-                       clocks = <&xo-27mhz>;
-                       reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
-                       vdd-supply = <&3v3-reg>;
-                       #clock-cells = <1>;
-               };
-       };
-
-       // Clock consumer node
-
-       foo@0 {
-               compatible = "bar,foo";
-               /* ... */
-               clock-names = "foo-input-clk";
-               clocks = <&max9485 MAX9485_CLKOUT1>;
-       };
diff --git a/Documentation/devicetree/bindings/clock/maxim,max9485.yaml b/Documentation/devicetree/bindings/clock/maxim,max9485.yaml
new file mode 100644 (file)
index 0000000..f9d8941
--- /dev/null
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/maxim,max9485.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Maxim MAX9485 Programmable Audio Clock Generator
+
+maintainers:
+  - Daniel Mack <daniel@zonque.org>
+
+description: >
+  Maxim MAX9485 Programmable Audio Clock Generator exposes 4 clocks in total:
+
+    - MAX9485_MCLKOUT:  A gated, buffered output of the input clock of 27 MHz
+    - MAX9485_CLKOUT:   A PLL that can be configured to 16 different discrete
+                        frequencies
+    - MAX9485_CLKOUT[1,2]:  Two gated outputs for MAX9485_CLKOUT
+
+  MAX9485_CLKOUT[1,2] are children of MAX9485_CLKOUT which upchain all rate set
+  requests.
+
+properties:
+  compatible:
+    const: maxim,max9485
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: Input clock. Must provide 27 MHz
+    maxItems: 1
+
+  clock-names:
+    items:
+      - const: xclk
+
+  '#clock-cells':
+    const: 1
+
+  reset-gpios:
+    description: >
+      GPIO descriptor connected to the #RESET input pin
+
+  vdd-supply:
+    description: A regulator node for Vdd
+
+  clock-output-names:
+    description: Name of output clocks, as defined in common clock bindings
+    items:
+      - const: mclkout
+      - const: clkout
+      - const: clkout1
+      - const: clkout2
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        clock-controller@63 {
+            compatible = "maxim,max9485";
+            reg = <0x63>;
+            #clock-cells = <1>;
+            clock-names = "xclk";
+            clocks = <&xo_27mhz>;
+            reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+            vdd-supply = <&reg_3v3>;
+        };
+    };