drm/amd/display: Remove min/max clock levels from clk_mgr (v2)

These fields are not used by anything anymore.

v2:
- Delete dm_pp_get_static_clocks()
- Delete pp_to_dc_powerlevel_state()

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Melissa Wen <mwen@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
index 17f42201ab8629cb7ce4d330bbd61dd9deb05160..a3ee580d8dd129a2782b20483e63d17bc063da86 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c
@@ -183,33 +183,6 @@ static enum amd_pp_clock_type dc_to_pp_clock_type(
        return amd_pp_clk_type;
 }
 
-static enum dm_pp_clocks_state pp_to_dc_powerlevel_state(
-                       enum PP_DAL_POWERLEVEL max_clocks_state)
-{
-       switch (max_clocks_state) {
-       case PP_DAL_POWERLEVEL_0:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_0;
-       case PP_DAL_POWERLEVEL_1:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_1;
-       case PP_DAL_POWERLEVEL_2:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_2;
-       case PP_DAL_POWERLEVEL_3:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_3;
-       case PP_DAL_POWERLEVEL_4:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_4;
-       case PP_DAL_POWERLEVEL_5:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_5;
-       case PP_DAL_POWERLEVEL_6:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_6;
-       case PP_DAL_POWERLEVEL_7:
-               return DM_PP_CLOCKS_DPM_STATE_LEVEL_7;
-       default:
-               DRM_ERROR("DM_PPLIB: invalid powerlevel state: %d!\n",
-                               max_clocks_state);
-               return DM_PP_CLOCKS_STATE_INVALID;
-       }
-}
-
 static void pp_to_dc_clock_levels(
                const struct amd_pp_clocks *pp_clks,
                struct dm_pp_clock_levels *dc_clks,
@@ -438,23 +411,6 @@ bool dm_pp_apply_clock_for_voltage_request(
        return true;
 }
 
-bool dm_pp_get_static_clocks(
-       const struct dc_context *ctx,
-       struct dm_pp_static_clock_info *static_clk_info)
-{
-       struct amdgpu_device *adev = ctx->driver_context;
-       struct amd_pp_clock_info pp_clk_info = {0};
-
-       if (amdgpu_dpm_get_current_clocks(adev, &pp_clk_info))
-               return false;
-
-       static_clk_info->max_clocks_state = pp_to_dc_powerlevel_state(pp_clk_info.max_clocks_state);
-       static_clk_info->max_mclk_khz = pp_clk_info.max_memory_clock * 10;
-       static_clk_info->max_sclk_khz = pp_clk_info.max_engine_clock * 10;
-
-       return true;
-}
-
 static void pp_rv_set_wm_ranges(struct pp_smu *pp,
                struct pp_smu_wm_range_sets *ranges)
 {

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
index e8daee975b790689397e6e81b8e0af4a2af46391..b7b72af9570ae1fc98e19c50680424ba1ef9df65 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -257,11 +257,6 @@ int dce_set_clock(
                actual_clock = pxl_clk_params.dfs_bypass_display_clock;
        }
 
-       /* from power down, we need mark the clock state as ClocksStateNominal
-        * from HWReset, so when resume we will call pplib voltage regulator.*/
-       if (requested_clk_khz == 0)
-               clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
        if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu))
                dmcu->funcs->set_psr_wait_loop(dmcu, actual_clock / 1000 / 7);
 
@@ -425,7 +420,6 @@ void dce_clk_mgr_construct(
                struct clk_mgr_internal *clk_mgr)
 {
        struct clk_mgr *base = &clk_mgr->base;
-       struct dm_pp_static_clock_info static_clk_info = {0};
 
        if (ctx->dce_version <= DCE_VERSION_6_4)
                memcpy(clk_mgr->max_clks_by_state,
@@ -451,14 +445,6 @@ void dce_clk_mgr_construct(
        clk_mgr->dprefclk_ss_divider = 1000;
        clk_mgr->ss_on_dprefclk = false;
 
-       if (ctx->dce_version >= DCE_VERSION_8_0) {
-               if (dm_pp_get_static_clocks(ctx, &static_clk_info))
-                       clk_mgr->max_clks_state = static_clk_info.max_clocks_state;
-               else
-                       clk_mgr->max_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-               clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_INVALID;
-       }
-
        base->clks.max_supported_dispclk_khz =
                clk_mgr->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
 

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
index 48393c69735b674c07d6cbc204a743f68a31f4a0..0f3f8df4df96a3a46715925e88d46f4e492255c7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c
@@ -89,13 +89,6 @@ int dce112_set_clock(struct clk_mgr *clk_mgr_base, int requested_clk_khz)
        bp->funcs->set_dce_clock(bp, &dce_clk_params);
        actual_clock = dce_clk_params.target_clock_frequency;
 
-       /*
-        * from power down, we need mark the clock state as ClocksStateNominal
-        * from HWReset, so when resume we will call pplib voltage regulator.
-        */
-       if (requested_clk_khz == 0)
-               clk_mgr_dce->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
        /*Program DP ref Clock*/
        /*VBIOS will determine DPREFCLK frequency, so we don't set it*/
        dce_clk_params.target_clock_frequency = 0;
@@ -143,14 +136,6 @@ int dce112_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_clk_khz)
        bp->funcs->set_dce_clock(bp, &dce_clk_params);
        actual_clock = dce_clk_params.target_clock_frequency;
 
-       /*
-        * from power down, we need mark the clock state as ClocksStateNominal
-        * from HWReset, so when resume we will call pplib voltage regulator.
-        */
-       if (requested_clk_khz == 0)
-               clk_mgr->cur_min_clks_state = DM_PP_CLOCKS_STATE_NOMINAL;
-
-
        if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
                if (clk_mgr->dfs_bypass_disp_clk != actual_clock)
                        dmcu->funcs->set_psr_wait_loop(dmcu,

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 1395d36bfabe9dce089729f047246bcedf1fd15e..8b062b011fc65ab915e6cd7308e4f80d5649e6c8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -228,10 +228,6 @@ bool dm_pp_apply_clock_for_voltage_request(
        const struct dc_context *ctx,
        struct dm_pp_clock_for_voltage_req *clock_for_voltage_req);
 
-bool dm_pp_get_static_clocks(
-       const struct dc_context *ctx,
-       struct dm_pp_static_clock_info *static_clk_info);
-
 /****** end of PP interfaces ******/
 
 struct persistent_data_flag {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
index c69ccfcebeb5ac0efae17eb4072bdebec95feb1a..e01bf6bd7f3f4f2931ea21685da8e7254a26ea6d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h
@@ -477,8 +477,6 @@ struct clk_mgr_internal {
         */
        int dprefclk_ss_divider;
 
-       enum dm_pp_clocks_state max_clks_state;
-       enum dm_pp_clocks_state cur_min_clks_state;
        bool periodic_retraining_disabled;
 
        unsigned int cur_phyclk_req_table[MAX_LINKS];