]> git.ipfire.org Git - thirdparty/kernel/stable.git/commitdiff
spi: spi-fsl-lpspi: Clear status register after disabling the module
authorLarisa Grigore <larisa.grigore@nxp.com>
Thu, 28 Aug 2025 10:14:43 +0000 (11:14 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 9 Sep 2025 16:56:33 +0000 (18:56 +0200)
[ Upstream commit dedf9c93dece441e9a0a4836458bc93677008ddd ]

Clear the error flags after disabling the module to avoid the case when
a flag is set again between flag clear and module disable. And use
SR_CLEAR_MASK to replace hardcoded value for improved readability.

Although fsl_lpspi_reset() was only introduced in commit a15dc3d657fa
("spi: lpspi: Fix CLK pin becomes low before one transfer"), the
original driver only reset SR in the interrupt handler, making it
vulnerable to the same issue. Therefore the fixes commit is set at the
introduction of the driver.

Fixes: 5314987de5e5 ("spi: imx: add lpspi bus driver")
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Ciprian Marian Costea <ciprianmarian.costea@nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Link: https://patch.msgid.link/20250828-james-nxp-lpspi-v2-4-6262b9aa9be4@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/spi/spi-fsl-lpspi.c

index d437ed1349edb999bba792936bdc6fca4dc127ea..8ef82a11ebb0fa0245bed91942d499604fe18ce4 100644 (file)
@@ -83,6 +83,8 @@
 #define TCR_RXMSK      BIT(19)
 #define TCR_TXMSK      BIT(18)
 
+#define SR_CLEAR_MASK  GENMASK(13, 8)
+
 struct fsl_lpspi_devtype_data {
        u8 prescale_max;
 };
@@ -532,14 +534,13 @@ static int fsl_lpspi_reset(struct fsl_lpspi_data *fsl_lpspi)
                fsl_lpspi_intctrl(fsl_lpspi, 0);
        }
 
-       /* W1C for all flags in SR */
-       temp = 0x3F << 8;
-       writel(temp, fsl_lpspi->base + IMX7ULP_SR);
-
        /* Clear FIFO and disable module */
        temp = CR_RRF | CR_RTF;
        writel(temp, fsl_lpspi->base + IMX7ULP_CR);
 
+       /* W1C for all flags in SR */
+       writel(SR_CLEAR_MASK, fsl_lpspi->base + IMX7ULP_SR);
+
        return 0;
 }